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SINGLE BUFFER/DRIVER. SN74AUC1G240 Datasheet

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SINGLE BUFFER/DRIVER. SN74AUC1G240 Datasheet






SN74AUC1G240 BUFFER/DRIVER. Datasheet pdf. Equivalent




SN74AUC1G240 BUFFER/DRIVER. Datasheet pdf. Equivalent





Part

SN74AUC1G240

Description

SINGLE BUFFER/DRIVER



Feature


www.ti.com SN74AUC1G240 SINGLE BUFFER/D RIVER WITH 3-STATE OUTPUT SCES384I – MARCH 2002 – REVISED FEBRUARY 2007 F EATURES • Available in the Texas Ins truments NanoFree™ Package • Optimi zed for 1.8-V Operation and Is 3.6-V I/ O Tolerant to Support Mixed-Mode Signal Operation • Ioff Supports Partial-Po wer-Down Mode Operation • Sub-1-V Ope rable • Max tpd of 2.5 ns at 1.8.
Manufacture

Texas Instruments

Datasheet
Download SN74AUC1G240 Datasheet


Texas Instruments SN74AUC1G240

SN74AUC1G240; V DBV PACKAGE (TOP VIEW) • Low Power Consumption, 10-µA Max ICC • ±8-mA Output Drive at 1.8 V • Latch-Up Per formance Exceeds 100 mA Per JESD 78, Cl ass II • ESD Protection Exceeds JESD 22 – 2000-V Human-Body Model (A114-A) – 200-V Machine Model (A115-A) – 1 000-V Charged-Device Model (C101) DCK PACKAGE (TOP VIEW) YZP PACKAGE (BOTTOM VIEW) OE 1 A 2 OE 1 5 VCC.


Texas Instruments SN74AUC1G240

GND 3 4 Y 5 VCC A2 A 2 OE 1 5 VC C GND 3 4Y GND 3 4 Y See mechan ical drawings for dimensions. DESCRIPT ION/ORDERING INFORMATION This bus buffe r gate is operational at 0.8-V to 2.7-V VCC, but is designed specifically for 1.65-V to 1.95-V VCC operation. The SN7 4AUC1G240 is a single line driver with a 3-state output. The output is disable d when the output-.


Texas Instruments SN74AUC1G240

enable (OE) input is high. To ensure the high-impedance state during power up o r power down, OE should be tied to VCC through a pullup resistor; the minimum value of the resistor is determined by the current-sinking capability of the d river. NanoFree™ package technology i s a major breakthrough in IC packaging concepts, using the die as the package. This device is full.

Part

SN74AUC1G240

Description

SINGLE BUFFER/DRIVER



Feature


www.ti.com SN74AUC1G240 SINGLE BUFFER/D RIVER WITH 3-STATE OUTPUT SCES384I – MARCH 2002 – REVISED FEBRUARY 2007 F EATURES • Available in the Texas Ins truments NanoFree™ Package • Optimi zed for 1.8-V Operation and Is 3.6-V I/ O Tolerant to Support Mixed-Mode Signal Operation • Ioff Supports Partial-Po wer-Down Mode Operation • Sub-1-V Ope rable • Max tpd of 2.5 ns at 1.8.
Manufacture

Texas Instruments

Datasheet
Download SN74AUC1G240 Datasheet




 SN74AUC1G240
www.ti.com
SN74AUC1G240
SINGLE BUFFER/DRIVER
WITH 3-STATE OUTPUT
SCES384I – MARCH 2002 – REVISED FEBRUARY 2007
FEATURES
Available in the Texas Instruments
NanoFree™ Package
Optimized for 1.8-V Operation and Is 3.6-V I/O
Tolerant to Support Mixed-Mode Signal
Operation
Ioff Supports Partial-Power-Down Mode
Operation
Sub-1-V Operable
Max tpd of 2.5 ns at 1.8 V
DBV PACKAGE
(TOP VIEW)
Low Power Consumption, 10-µA Max ICC
• ±8-mA Output Drive at 1.8 V
Latch-Up Performance Exceeds 100 mA Per
JESD 78, Class II
ESD Protection Exceeds JESD 22
– 2000-V Human-Body Model (A114-A)
– 200-V Machine Model (A115-A)
– 1000-V Charged-Device Model (C101)
DCK PACKAGE
(TOP VIEW)
YZP PACKAGE
(BOTTOM VIEW)
OE
1
A
2
OE
1
5
VCC
GND 3 4 Y
5
VCC
A2
A
2
OE 1 5 VCC
GND
3
4Y
GND
3
4
Y
See mechanical drawings for dimensions.
DESCRIPTION/ORDERING INFORMATION
This bus buffer gate is operational at 0.8-V to 2.7-V VCC, but is designed specifically for 1.65-V to 1.95-V VCC
operation.
The SN74AUC1G240 is a single line driver with a 3-state output. The output is disabled when the output-enable
(OE) input is high.
To ensure the high-impedance state during power up or power down, OE should be tied to VCC through a pullup
resistor; the minimum value of the resistor is determined by the current-sinking capability of the driver.
NanoFree™ package technology is a major breakthrough in IC packaging concepts, using the die as the
package.
This device is fully specified for partial-power-down applications using Ioff. The Ioff circuitry disables the outputs,
preventing damaging current backflow through the device when it is powered down.
ORDERING INFORMATION
TA
–40°C to 85°C
PACKAGE (1)
NanoFree™ – WCSP (DSBGA)
0.23-mm Large Bump – YZP (Pb-free)
SOT (SOT-23) – DBV
Reel of 3000
Reel of 3000
ORDERABLE PART NUMBER TOP-SIDE MARKING(2)
SN74AUC1G240YZPR
_ _ _UK_
SN74AUC1G240DBVR
U40_
SOT (SC-70) – DCK
Reel of 3000 SN74AUC1G240DCKR
UK_
(1) Package drawings, standard packing quantities, thermal data, symbolization, and PCB design guidelines are available at
www.ti.com/sc/package.
(2) DBV/DCK: The actual top-side marking has one additional character that designates the assembly/test site.
YZP: The actual top-side marking has three preceding characters to denote year, month, and sequence code, and one following
character to designate the assembly/test site.
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas
Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
NanoFree is a trademark of Texas Instruments.
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of the Texas
Instruments standard warranty. Production processing does not
necessarily include testing of all parameters.
Copyright © 2002–2007, Texas Instruments Incorporated




 SN74AUC1G240
SN74AUC1G240
SINGLE BUFFER/DRIVER
WITH 3-STATE OUTPUT
SCES384I – MARCH 2002 – REVISED FEBRUARY 2007
FUNCTION TABLE
INPUTS
OE
A
L
H
L
L
H
X
OUTPUT
Y
L
H
Z
LOGIC DIAGRAM (POSITIVE LOGIC)
1
OE
2
A
4
Y
www.ti.com
Absolute Maximum Ratings(1)
over operating free-air temperature range (unless otherwise noted)
VCC
Supply voltage range
VI
Input voltage range(2)
VO
Voltage range applied to any output in the high-impedance or power-off state(2)
VO
Output voltage range(2)
IIK
Input clamp current
VI < 0
IOK
Output clamp current
VO < 0
IO
Continuous output current
Continuous current through VCC or GND
DBV package
θJA
Package thermal impedance(3)
DCK package
YZP package
Tstg
Storage temperature range
MIN
MAX
–0.5
3.6
–0.5
3.6
–0.5
3.6
–0.5 VCC + 0.5
–50
–50
±20
±100
206
252
132
–65
150
UNIT
V
V
V
V
mA
mA
mA
mA
°C/W
°C
(1) Stresses beyond those listed under "absolute maximum ratings" may cause permanent damage to the device. These are stress ratings
only, and functional operation of the device at these or any other conditions beyond those indicated under "recommended operating
conditions" is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
(2) The input negative-voltage and output voltage ratings may be exceeded if the input and output current ratings are observed.
(3) The package thermal impedance is calculated in accordance with JESD 51-7.
2
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 SN74AUC1G240
www.ti.com
Recommended Operating Conditions(1)
SN74AUC1G240
SINGLE BUFFER/DRIVER
WITH 3-STATE OUTPUT
SCES384I – MARCH 2002 – REVISED FEBRUARY 2007
VCC
Supply voltage
VIH
High-level input voltage
VIL
Low-level input voltage
VI
Input voltage
VO
Output voltage
IOH
High-level output current
IOL
Low-level output current
t/v Input transition rise or fall rate
TA
Operating free-air temperature
VCC = 0.8 V
VCC = 1.1 V to 1.95 V
VCC = 2.3 V to 2.7 V
VCC = 0.8 V
VCC = 1.1 V to 1.95 V
VCC = 2.3 V to 2.7 V
VCC = 0.8 V
VCC = 1.1 V
VCC = 1.4 V
VCC = 1.65 V
VCC = 2.3 V
VCC = 0.8 V
VCC = 1.1 V
VCC = 1.4 V
VCC = 1.65 V
VCC = 2.3 V
VCC = 0.8 V to 1.6 V
VCC = 1.65 V to 1.95 V
VCC = 2.3 V to 2.7 V
MIN
MAX UNIT
0.8
2.7 V
VCC
0.65 VCC
V
1.7
0
0.35 VCC V
0.7
0
3.6 V
0
VCC
V
–0.7
–3
–5 mA
–8
–9
0.7
3
5 mA
8
9
20
10 ns/V
3
–40
85 °C
(1) All unused inputs of the device must be held at VCC or GND to ensure proper device operation. Refer to the TI application report,
Implications of Slow or Floating CMOS Inputs, literature number SCBA004.
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3



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