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D-type Flip-Flop. SN74AUC1G79 Datasheet

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D-type Flip-Flop. SN74AUC1G79 Datasheet






SN74AUC1G79 Flip-Flop. Datasheet pdf. Equivalent




SN74AUC1G79 Flip-Flop. Datasheet pdf. Equivalent





Part

SN74AUC1G79

Description

Single Positive-Edge-Triggered D-type Flip-Flop



Feature


Product Folder Order Now Technical Doc uments Tools & Software Support & Com munity SN74AUC1G79 SCES387L – MARCH 2002 – REVISED JUNE 2017 SN74AUC1G79 Single Positive-Edge-Triggered D-type F lip-Flop 1 Features •1 Latch-Up Perf ormance Exceeds 100 mA Per JESD 78, Cla ss II • ESD Protection Exceeds JESD 2 2 – 2000-V Human-Body Model (A114-A) – 200-V Machine Model (A115-.
Manufacture

Texas Instruments

Datasheet
Download SN74AUC1G79 Datasheet


Texas Instruments SN74AUC1G79

SN74AUC1G79; A) – 1000-V Charged-Device Model (C101 ) • Available in the Texas Instrument s NanoFree™ Package • Optimized for 1.8-V Operation and Is 3.6-V I/O Toler ant to Support Mixed-Mode Signal Operat ion • Ioff Supports Partial-Power-Dow n Mode Operation • Sub-1-V Operable Max tpd of 1.9 ns at 1.8 V • Low P ower Consumption, 10-µA Maximum ICC ±8-mA Output Drive at 1.8 V 2 Appli.


Texas Instruments SN74AUC1G79

cations • AV Receiver • Audio Dock: Portable • Blu-Ray Player and Home Th eater • Embedded PC • MP3 Player/Re corder (Portable Audio) • Personal Di gital Assistant (PDA) • Power: Teleco m/Server AC/DC Supply: Single Controlle r: Analog and Digital • Solid State D rive (SSD): Client and Enterprise • T V: LCD/Digital and High-Definition (HDT V) • Tablet: Enterprise • Video Anal.


Texas Instruments SN74AUC1G79

ytics: Server • Wireless Headset, Keyb oard, and Mouse 3 Description This sin gle positive-edge-triggered D-type flip -flop is operational at 0.8-V to 2.7-V VCC, but is designed specifically for 1 .65-V to 1.95-V VCC operation. When dat a at the data (D) input meets the setup time requirement, the data is transfer red to the Q output on the positive-goi ng edge of the clock.

Part

SN74AUC1G79

Description

Single Positive-Edge-Triggered D-type Flip-Flop



Feature


Product Folder Order Now Technical Doc uments Tools & Software Support & Com munity SN74AUC1G79 SCES387L – MARCH 2002 – REVISED JUNE 2017 SN74AUC1G79 Single Positive-Edge-Triggered D-type F lip-Flop 1 Features •1 Latch-Up Perf ormance Exceeds 100 mA Per JESD 78, Cla ss II • ESD Protection Exceeds JESD 2 2 – 2000-V Human-Body Model (A114-A) – 200-V Machine Model (A115-.
Manufacture

Texas Instruments

Datasheet
Download SN74AUC1G79 Datasheet




 SN74AUC1G79
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SN74AUC1G79
SCES387L – MARCH 2002 – REVISED JUNE 2017
SN74AUC1G79 Single Positive-Edge-Triggered D-type Flip-Flop
1 Features
1 Latch-Up Performance Exceeds 100 mA Per
JESD 78, Class II
• ESD Protection Exceeds JESD 22
– 2000-V Human-Body Model (A114-A)
– 200-V Machine Model (A115-A)
– 1000-V Charged-Device Model (C101)
• Available in the Texas Instruments NanoFree™
Package
• Optimized for 1.8-V Operation and Is 3.6-V I/O
Tolerant to Support Mixed-Mode Signal Operation
• Ioff Supports Partial-Power-Down Mode Operation
• Sub-1-V Operable
• Max tpd of 1.9 ns at 1.8 V
• Low Power Consumption, 10-µA Maximum ICC
• ±8-mA Output Drive at 1.8 V
2 Applications
• AV Receiver
• Audio Dock: Portable
• Blu-Ray Player and Home Theater
• Embedded PC
• MP3 Player/Recorder (Portable Audio)
• Personal Digital Assistant (PDA)
• Power: Telecom/Server AC/DC Supply: Single
Controller: Analog and Digital
• Solid State Drive (SSD): Client and Enterprise
• TV: LCD/Digital and High-Definition (HDTV)
• Tablet: Enterprise
• Video Analytics: Server
• Wireless Headset, Keyboard, and Mouse
3 Description
This single positive-edge-triggered D-type flip-flop is
operational at 0.8-V to 2.7-V VCC, but is designed
specifically for 1.65-V to 1.95-V VCC operation.
When data at the data (D) input meets the setup time
requirement, the data is transferred to the Q output
on the positive-going edge of the clock pulse. Clock
triggering occurs at a voltage level and is not directly
related to the rise time of the clock pulse. Following
the hold-time interval, data at the D input can be
changed without affecting the levels at the outputs.
NanoFree™ package technology is a major
breakthrough in IC packaging concepts, using the die
as the package.
This device is fully specified for partial-power-down
applications using Ioff. The Ioff circuitry disables the
outputs, preventing damaging current backflow
through the device when it is powered down.
Device Information(1)
PART NUMBER
PACKAGE
BODY SIZE (NOM)
SN74AUC1G79DBV SOT-23 (5)
2.90 mm × 1.60 mm
SN74AUC1G79DCK SC70 (5)
2.00 mm × 1.25 mm
SN74AUC1G79YZP DSBGA (5)
1.75 mm × 1.25 mm
(1) For all available packages, see the orderable addendum at
the end of the data sheet.
Logic Diagram (Positive Logic)
CLK
D
CLK
Q
Q
D
1
An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications,
intellectual property matters and other important disclaimers. UNLESS OTHERWISE NOTED, this document contains PRODUCTION
DATA.




 SN74AUC1G79
SN74AUC1G79
SCES387L – MARCH 2002 – REVISED JUNE 2017
www.ti.com
Table of Contents
1 Features .................................................................. 1
2 Applications ........................................................... 1
3 Description ............................................................. 1
4 Revision History..................................................... 2
5 Pin Configuration and Functions ......................... 3
6 Specifications......................................................... 4
6.1 Absolute Maximum Ratings ..................................... 4
6.2 ESD Ratings.............................................................. 4
6.3 Recommended Operating Conditions....................... 4
6.4 Thermal Information .................................................. 5
6.5 Electrical Characteristics........................................... 5
6.6 Timing Requirements ................................................ 5
6.7 Switching Characteristics: CL = 15 pF ...................... 6
6.8 Switching Characteristics: CL = 30 pF ...................... 6
6.9 Operating Characteristics.......................................... 6
7 Parameter Measurement Information .................. 7
8 Detailed Description .............................................. 8
8.1 Functional Block Diagram ......................................... 8
8.2 Device Functional Modes.......................................... 8
9 Device and Documentation Support.................... 9
9.1 Documentation Support ............................................ 9
9.2 Receiving Notification of Documentation Updates.... 9
9.3 Community Resources.............................................. 9
9.4 Trademarks ............................................................... 9
9.5 Electrostatic Discharge Caution ................................ 9
9.6 Glossary .................................................................... 9
10 Mechanical, Packaging, and Orderable
Information ............................................................. 9
4 Revision History
Changes from Revision K (April 2007) to Revision L
Page
• Deleted DRY package throughout data sheet........................................................................................................................ 1
• Added Applications, Device Information table, Pin Configuration and Functions, ESD Ratings table, Thermal
Information table, Feature Description section, Device Functional Modes, Device and Documentation Support
section, and Mechanical, Packaging, and Orderable Information section.............................................................................. 1
• Deleted Ordering Information table, see Mechanical, Packaging, and Orderable Information at the end of the data
sheet ...................................................................................................................................................................................... 1
• Changed pin names in the pinout diagram for the YZP package, from: "A" to:"D," from:"B" to:"CLK," and from:"Y" to: "Q" 3
2
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Copyright © 2002–2017, Texas Instruments Incorporated
Product Folder Links: SN74AUC1G79




 SN74AUC1G79
www.ti.com
5 Pin Configuration and Functions
DBV Package
5-Pin SOT-23
Top View
D
1
5
VCC
CLK
2
GND
3
4
Q
See mechanical drawings for dimensions.
PIN
I/O
NAME
DBV, DCK
YZP
CLK
2
B1
I
D
1
A1
I
GND
3
C1
Q
4
C2
O
VCC
5
A2
YZP Package
5-Pin DSBGA
Bottom View
1
2
C
GND
Q
B
CLK
A
D
VCC
Not to scale
Pin Functions
Clock input
Data input
Ground
Latched output
Positive supply
SN74AUC1G79
SCES387L – MARCH 2002 – REVISED JUNE 2017
DCK Package
5-Pin SC70
Top View
D
1
CLK
2
5
VCC
GND 3
4Q
DESCRIPTION
Copyright © 2002–2017, Texas Instruments Incorporated
Product Folder Links: SN74AUC1G79
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