SN74AUC32244

SN74AUC32244 32ĆBIT BUFFER/DRIVER WITH 3ĆSTATE OUTPUTS SCES425 − FEBRUARY 2003 D Member of the Texas Instruments Widebus+ Family D Optimized for 1.8-V Operation and is 3.6-V I/O Tolerant to Support Mixed-Mode Signal Operation D Ioff Supports Partial-Power-Down Mode Operation D Sub 1-V Operable D Max tpd of 1.8 ns at 1.8 V D Low Power Consumption, 40-µA Max ICC D ±8-mA Output Drive at 1.8 V D Latch-Up Performance Exceeds 100 mA Per JESD 78, Class II D ESD Protection Exceeds JESD 22 − 2000-V Human-Body Model (A114-A) − 200-V Machine Model (A115-A) − 1000-V Charged-Device Model (C101) description/ordering information This 32-bit buffer/driver is operational at 0.8-V to 2.7-V VCC, but is designed specifically for 1.65-V to 1.95-V VCC operation. The SN74AUC32244 is designed specifically to improve the performance and density of 3-state memory address drivers, clock drivers, and bus-oriented receivers and transmitters. The device can be used as eight 4-bit buffers, four 8-bit buffers, two 16-bit buffers, or one 32-bit buffer. It provides true outputs and symmetrical active-low output-enable (OE) inputs. To ensure the high-impedance state during power up or power down, OE should be tied to VCC through a pullup resistor; the minimum value of the resistor is determined by the current-sinking capability of the driver. This device is fully specified for partial-power-down applications using Ioff. The Ioff circuitry disables the outputs, preventing damaging current backflow through ...