DUAL POSITIVE-EDGE-TRIGGERED D-TYPE FLIP-FLOP
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SN74AUC74 DUAL POSITIVE-EDGE-TRIGGERED D-TYPE FLIP-FLOP
WITH CLEAR AND PRESET
SCES483A – AUGUST 2003 – REVIS...
Description
www.ti.com
SN74AUC74 DUAL POSITIVE-EDGE-TRIGGERED D-TYPE FLIP-FLOP
WITH CLEAR AND PRESET
SCES483A – AUGUST 2003 – REVISED MARCH 2005
FEATURES
Optimized for 1.8-V Operation and Is 3.6-V I/O Tolerant to Support Mixed-Mode Signal Operation
Ioff Supports Partial-Power-Down Mode Operation
Sub-1-V Operable Max tpd of 1.8 ns at 1.8 V Low Power Consumption, 10-µA Max ICC ±8-mA Output Drive at 1.8 V Latch-Up Performance Exceeds 100 mA Per
JESD 78, Class II
ESD Protection Exceeds JESD 22 – 2000-V Human-Body Model (A114-A)
– 200-V Machine Model (A115-A)
– 1000-V Charged-Device Model (C101)
GND 2Q
RGY PACKAGE (TOP VIEW)
1CLR VCC
1 1D 2 1CLK 3 1PRE 4 1Q 5 1Q 6
7
14 13 2CLR 12 2D 11 2CLK 10 2PRE 9 2Q
8
DESCRIPTION/ORDERING INFORMATION
This dual positive-edge-triggered D-type flip-flop is operational at 0.8-V to 2.7-V VCC, but is designed specifically for 1.65-V to 1.95-V VCC operation.
A low level at the preset (PRE) or clear (CLR) inputs sets or resets the outputs, regardless of the levels of the other inputs. When PRE and CLR are inactive (high), data at the data (D) input meeting the setup time requirements is transferred to the outputs on the positive-going edge of the clock pulse. Clock triggering occurs at a voltage level and is not directly related to the rise time of the clock pulse. Following the hold-time interval, data at the D input can be changed without affecting the levels at the outputs. To better optimize the flip-flop for higher frequencies, the CL...
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