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16-BIT BUFFER/DRIVER. SN74AUCH16244 Datasheet

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16-BIT BUFFER/DRIVER. SN74AUCH16244 Datasheet






SN74AUCH16244 BUFFER/DRIVER. Datasheet pdf. Equivalent




SN74AUCH16244 BUFFER/DRIVER. Datasheet pdf. Equivalent





Part

SN74AUCH16244

Description

16-BIT BUFFER/DRIVER



Feature


SN74AUCH16244 16-BIT BUFFER/DRIVER WITH 3-STATE OUTPUTS SCES391E – MARCH 2002 – REVISED DECEMBER 2002 D Member of the Texas Instruments Widebus Famil y D Optimized for 1.8-V Operation and i s 3.6-V I/O Tolerant to Support Mixed-M ode Signal Operation D Ioff Supports Pa rtial-Power-Down Mode Operation D Sub 1 -V Operable D Max tpd of 1.8 ns at 1.8 V D Low Power Consumptio.
Manufacture

Texas Instruments

Datasheet
Download SN74AUCH16244 Datasheet


Texas Instruments SN74AUCH16244

SN74AUCH16244; n, 20-µA Max ICC D ±8-mA Output Drive at 1.8 V D Bus Hold on Data Inputs Elim inates the Need for External Pullup/Pul ldown Resistors D Latch-Up Performance Exceeds 100 mA Per JESD 78, Class II D ESD Protection Exceeds JESD 22 – 2000 -V Human-Body Model (A114-A) – 200-V Machine Model (A115-A) – 1000-V Charg ed-Device Model (C101) description/orde ring information This 16-b.


Texas Instruments SN74AUCH16244

it buffer/driver is operational at 0.8-V to 2.7-V VCC, but is designed specific ally for 1.65-V to 1.95-V VCC operation . The SN74AUCH16244 is designed specifi cally to improve the performance and de nsity of 3-state memory address drivers , clock drivers, and bus-oriented recei vers and transmitters. DGG OR DGV PACK AGE (TOP VIEW) 1OE 1 1Y1 2 1Y2 3 GND 4 1Y3 5 1Y4 6 VCC 7.


Texas Instruments SN74AUCH16244

2Y1 8 2Y2 9 GND 10 2Y3 11 2Y4 12 3Y1 13 3Y2 14 GND 15 3Y3 16 3Y4 17 VCC 18 4Y1 19 4Y2 20 GND 21 4Y3 22 4Y4 23 4OE 24 48 2OE 47 1A1 46 1A2 45 GND 44 1A3 43 1A4 42 VCC 41 2A1 40 2A2 39 GND 38 2A3 37 2A4 36 3A1 35 3A2 34 GND 33 3A3 32 3 A4 31 VCC 30 4A1 29 4A2 28 GND 27 4A3 2 6 4A4 25 3OE The device can be used as four 4-bit buffers, two 8-bit buffers, or one 16-bit buf.

Part

SN74AUCH16244

Description

16-BIT BUFFER/DRIVER



Feature


SN74AUCH16244 16-BIT BUFFER/DRIVER WITH 3-STATE OUTPUTS SCES391E – MARCH 2002 – REVISED DECEMBER 2002 D Member of the Texas Instruments Widebus Famil y D Optimized for 1.8-V Operation and i s 3.6-V I/O Tolerant to Support Mixed-M ode Signal Operation D Ioff Supports Pa rtial-Power-Down Mode Operation D Sub 1 -V Operable D Max tpd of 1.8 ns at 1.8 V D Low Power Consumptio.
Manufacture

Texas Instruments

Datasheet
Download SN74AUCH16244 Datasheet




 SN74AUCH16244
SN74AUCH16244
16-BIT BUFFER/DRIVER
WITH 3-STATE OUTPUTS
SCES391E – MARCH 2002 – REVISED DECEMBER 2002
D Member of the Texas Instruments
WidebusFamily
D Optimized for 1.8-V Operation and is 3.6-V
I/O Tolerant to Support Mixed-Mode Signal
Operation
D Ioff Supports Partial-Power-Down Mode
Operation
D Sub 1-V Operable
D Max tpd of 1.8 ns at 1.8 V
D Low Power Consumption, 20-µA Max ICC
D ±8-mA Output Drive at 1.8 V
D Bus Hold on Data Inputs Eliminates the
Need for External Pullup/Pulldown
Resistors
D Latch-Up Performance Exceeds 100 mA Per
JESD 78, Class II
D ESD Protection Exceeds JESD 22
– 2000-V Human-Body Model (A114-A)
– 200-V Machine Model (A115-A)
– 1000-V Charged-Device Model (C101)
description/ordering information
This 16-bit buffer/driver is operational at 0.8-V to
2.7-V VCC, but is designed specifically for 1.65-V
to 1.95-V VCC operation.
The SN74AUCH16244 is designed specifically to
improve the performance and density of 3-state
memory address drivers, clock drivers, and
bus-oriented receivers and transmitters.
DGG OR DGV PACKAGE
(TOP VIEW)
1OE 1
1Y1 2
1Y2 3
GND 4
1Y3 5
1Y4 6
VCC 7
2Y1 8
2Y2 9
GND 10
2Y3 11
2Y4 12
3Y1 13
3Y2 14
GND 15
3Y3 16
3Y4 17
VCC 18
4Y1 19
4Y2 20
GND 21
4Y3 22
4Y4 23
4OE 24
48 2OE
47 1A1
46 1A2
45 GND
44 1A3
43 1A4
42 VCC
41 2A1
40 2A2
39 GND
38 2A3
37 2A4
36 3A1
35 3A2
34 GND
33 3A3
32 3A4
31 VCC
30 4A1
29 4A2
28 GND
27 4A3
26 4A4
25 3OE
The device can be used as four 4-bit buffers, two 8-bit buffers, or one 16-bit buffer. It provides true outputs and
symmetrical active-low output-enable (OE) inputs.
To ensure the high-impedance state during power up or power down, OE should be tied to VCC through a pullup
resistor; the minimum value of the resistor is determined by the current-sinking capability of the driver.
ORDERING INFORMATION
TA
PACKAGE†
ORDERABLE
PART NUMBER
TOP-SIDE
MARKING
TSSOP – DGG Tape and reel SN74AUCH16244DGGR AUCH16244
–40°C to 85°C TVSOP – DGV Tape and reel SN74AUCH16244DGVR MJ244
VFBGA – GQL Tape and reel SN74AUCH16244GQLR MJ244
Package drawings, standard packing quantities, thermal data, symbolization, and PCB design
guidelines are available at www.ti.com/sc/package.
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
Widebus is a trademark of Texas Instruments.
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of Texas Instruments
standard warranty. Production processing does not necessarily include
testing of all parameters.
Copyright 2002, Texas Instruments Incorporated
POST OFFICE BOX 655303 DALLAS, TEXAS 75265
1




 SN74AUCH16244
SN74AUCH16244
16-BIT BUFFER/DRIVER
WITH 3-STATE OUTPUTS
SCES391E MARCH 2002 REVISED DECEMBER 2002
description/ordering information (continued)
Active bus-hold circuitry holds unused or undriven inputs at a valid logic state. Use of pullup or pulldown resistors
with the bus-hold circuitry is not recommended.
This device is fully specified for partial-power-down applications using Ioff. The Ioff circuitry disables the outputs,
preventing damaging current backflow through the device when it is powered down.
GQL PACKAGE
(TOP VIEW)
123456
A
B
C
D
E
F
G
H
J
K
terminal assignments
1
2
3
4
5
6
A
1OE
NC
NC
NC
NC
2OE
B
1Y2
1Y1
GND
GND
1A1
1A2
C
1Y4
1Y3
VCC
VCC
1A3
1A4
D
2Y2
2Y1
GND
GND
2A1
2A2
E
2Y4
2Y3
2A3
2A4
F
3Y1
3Y2
3A2
3A1
G
3Y3
3Y4
GND
GND
3A4
3A3
H
4Y1
4Y2
VCC
VCC
4A2
4A1
J
4Y3
4Y4
GND
GND
4A4
4A3
K
4OE
NC
NC
NC
NC
3OE
NC No internal connection
FUNCTION TABLE
(each 4-bit buffer)
INPUTS
OE
A
OUTPUT
Y
L
H
H
L
L
L
H
X
Z
2
POST OFFICE BOX 655303 DALLAS, TEXAS 75265




 SN74AUCH16244
logic diagram (positive logic)
1
1OE
47
1A1
46
1A2
1A3 44
1A4 43
SN74AUCH16244
16-BIT BUFFER/DRIVER
WITH 3-STATE OUTPUTS
SCES391E MARCH 2002 REVISED DECEMBER 2002
2
1Y1
3
1Y2
5 1Y3
6 1Y4
25
3OE
36
3A1
35
3A2
3A3 33
3A4 32
13
3Y1
14
3Y2
16 3Y3
17 3Y4
48
2OE
41
2A1
40
2A2
2A3 38
37
2A4
8
2Y1
9
2Y2
11 2Y3
12
2Y4
24
4OE
30
4A1
29
4A2
4A3 27
26
4A4
19
4Y1
20
4Y2
22 4Y3
23
4Y4
Pin numbers shown are for the DGG and DGV packages.
absolute maximum ratings over operating free-air temperature range (unless otherwise noted)
Supply voltage range, VCC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0.5 V to 3.6 V
Input voltage range, VI (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0.5 V to 3.6 V
Voltage range applied to any output in the high-impedance or power-off state, VO
(see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0.5 V to 3.6 V
Output voltage range, VO (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0.5 V to VCC + 0.5 V
Input clamp current, IIK (VI < 0) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50 mA
Output clamp current, IOK (VO < 0) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50 mA
Continuous output current, IO . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ±20 mA
Continuous current through VCC or GND . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ±100 mA
Package thermal impedance, θJA (see Note 2): DGG package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 70°C/W
DGV package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58°C/W
GQL package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42°C/W
Storage temperature range, Tstg . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 65°C to 150°C
Stresses beyond those listed under absolute maximum ratingsmay cause permanent damage to the device. These are stress ratings only, and
functional operation of the device at these or any other conditions beyond those indicated under recommended operating conditionsis not
implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
NOTES: 1. The input negative-voltage and output voltage ratings may be exceeded if the input and output current ratings are observed.
2. The package thermal impedance is calculated in accordance with JESD 51-7.
POST OFFICE BOX 655303 DALLAS, TEXAS 75265
3



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