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D-TYPE FLIP-FLOP. SN74AUCH32374 Datasheet

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D-TYPE FLIP-FLOP. SN74AUCH32374 Datasheet






SN74AUCH32374 FLIP-FLOP. Datasheet pdf. Equivalent




SN74AUCH32374 FLIP-FLOP. Datasheet pdf. Equivalent





Part

SN74AUCH32374

Description

32-BIT EDGE-TRIGGERED D-TYPE FLIP-FLOP



Feature


D Member of the Texas Instruments Widebu s+ Family D Optimized for 1.8-V Oper ation and is 3.6-V I/O Tolerant to Supp ort Mixed-Mode Signal Operation D Ioff Supports Partial-Power-Down Mode Operat ion D Sub 1-V Operable D Max tpd of 2.8 ns at 1.8 V D Low Power Consumption, 4 0-µA Max ICC SN74AUCH32374 32-BIT EDG E-TRIGGERED D-TYPE FLIP-FLOP WITH 3-STA TE OUTPUTS SCES476 – .
Manufacture

Texas Instruments

Datasheet
Download SN74AUCH32374 Datasheet


Texas Instruments SN74AUCH32374

SN74AUCH32374; AUGUST 2003 D ±8-mA Output Drive at 1.8 V D Bus Hold on Data Inputs Eliminates the Need for External Pullup/Pulldown Resistors D Latch-Up Performance Exceed s 100 mA Per JESD 78, Class II D ESD Pr otection Exceeds JESD 22 – 2000-V Hum an-Body Model (A114-A) – 200-V Machin e Model (A115-A) – 1000-V Charged-Dev ice Model (C101) description/ordering information This 32-bit .


Texas Instruments SN74AUCH32374

edge-triggered D-type flip-flop is opera tional at 0.8-V to 2.7-V VCC, but is de signed specifically for 1.65-V to 1.95- V VCC operation. The SN74AUCH32374 is p articularly suitable for implementing b uffer registers, I/O ports, bidirection al bus drivers, and working registers. It can be used as four 8-bit flip-flops , two 16-bit flip-flops, or one 32-bit flip-flop. On the .


Texas Instruments SN74AUCH32374

positive transition of the clock (CLK) i nput, the Q outputs of the flip-flop ta ke on the logic levels set up at the da ta (D) inputs. A buffered output-enable (OE) input can be used to place the ei ght outputs in either a normal logic st ate (high or low logic levels) or the h igh-impedance state. In the high-impeda nce state, the outputs neither load nor drive the bus lin.

Part

SN74AUCH32374

Description

32-BIT EDGE-TRIGGERED D-TYPE FLIP-FLOP



Feature


D Member of the Texas Instruments Widebu s+ Family D Optimized for 1.8-V Oper ation and is 3.6-V I/O Tolerant to Supp ort Mixed-Mode Signal Operation D Ioff Supports Partial-Power-Down Mode Operat ion D Sub 1-V Operable D Max tpd of 2.8 ns at 1.8 V D Low Power Consumption, 4 0-µA Max ICC SN74AUCH32374 32-BIT EDG E-TRIGGERED D-TYPE FLIP-FLOP WITH 3-STA TE OUTPUTS SCES476 – .
Manufacture

Texas Instruments

Datasheet
Download SN74AUCH32374 Datasheet




 SN74AUCH32374
D Member of the Texas Instruments
Widebus+Family
D Optimized for 1.8-V Operation and is 3.6-V
I/O Tolerant to Support Mixed-Mode Signal
Operation
D Ioff Supports Partial-Power-Down Mode
Operation
D Sub 1-V Operable
D Max tpd of 2.8 ns at 1.8 V
D Low Power Consumption, 40-µA Max ICC
SN74AUCH32374
32-BIT EDGE-TRIGGERED D-TYPE FLIP-FLOP
WITH 3-STATE OUTPUTS
SCES476 – AUGUST 2003
D ±8-mA Output Drive at 1.8 V
D Bus Hold on Data Inputs Eliminates the
Need for External Pullup/Pulldown
Resistors
D Latch-Up Performance Exceeds 100 mA Per
JESD 78, Class II
D ESD Protection Exceeds JESD 22
– 2000-V Human-Body Model (A114-A)
– 200-V Machine Model (A115-A)
– 1000-V Charged-Device Model (C101)
description/ordering information
This 32-bit edge-triggered D-type flip-flop is operational at 0.8-V to 2.7-V VCC, but is designed specifically for
1.65-V to 1.95-V VCC operation.
The SN74AUCH32374 is particularly suitable for implementing buffer registers, I/O ports, bidirectional bus
drivers, and working registers. It can be used as four 8-bit flip-flops, two 16-bit flip-flops, or one 32-bit flip-flop.
On the positive transition of the clock (CLK) input, the Q outputs of the flip-flop take on the logic levels set up
at the data (D) inputs.
A buffered output-enable (OE) input can be used to place the eight outputs in either a normal logic state (high
or low logic levels) or the high-impedance state. In the high-impedance state, the outputs neither load nor drive
the bus lines significantly. The high-impedance state and increased drive provide the capability to drive bus lines
without interface or pullup components.
OE does not affect internal operations of the latch. Old data can be retained or new data can be entered while
the outputs are in the high-impedance state.
To ensure the high-impedance state during power up or power down, OE should be tied to VCC through a pullup
resistor; the minimum value of the resistor is determined by the current-sinking capability of the driver.
Active bus-hold circuitry holds unused or undriven inputs at a valid logic state. Use of pullup or pulldown resistors
with the bus-hold circuitry is not recommended.
This device is fully specified for partial-power-down applications using Ioff. The Ioff circuitry disables the outputs,
preventing damaging current backflow through the device when it is powered down.
ORDERING INFORMATION
TA
PACKAGE†
ORDERABLE
PART NUMBER
TOP-SIDE
MARKING
–40°C to 85°C LFBGA – GKE
Tape and reel SN74AUCH32374GKER MK374
Package drawings, standard packing quantities, thermal data, symbolization, and PCB design guidelines
are available at www.ti.com/sc/package.
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
Widebus+ is a trademark of Texas Instruments.
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of Texas Instruments
standard warranty. Production processing does not necessarily include
testing of all parameters.
Copyright 2003, Texas Instruments Incorporated
POST OFFICE BOX 655303 DALLAS, TEXAS 75265
1




 SN74AUCH32374
SN74AUCH32374
32-BIT EDGE-TRIGGERED D-TYPE FLIP-FLOP
WITH 3-STATE OUTPUTS
SCES476 – AUGUST 2003
GKE PACKAGE
(TOP VIEW)
123456
A
B
C
D
E
F
G
H
J
K
L
M
N
P
R
T
terminal assignments
1
2
3
4
5
6
A
1Q2
1Q1
1OE
1CLK
1D1
1D2
B
1Q4
1Q3
GND
GND
1D3
1D4
C
1Q6
1Q5
VCC
VCC
1D5
1D6
D
1Q8
1Q7
GND
GND
1D7
1D8
E
2Q2
2Q1
GND
GND
2D1
2D2
F
2Q4
2Q3
VCC
VCC
2D3
2D4
G
2Q6
2Q5
GND
GND
2D5
2D6
H
2Q7
2Q8
2OE
2CLK
2D8
2D7
J
3Q2
3Q1
3OE
3CLK
3D1
3D2
K
3Q4
3Q3
GND
GND
3D3
3D4
L
3Q6
3Q5
VCC
VCC
3D5
3D6
M
3Q8
3Q7
GND
GND
3D7
3D8
N
4Q2
4Q1
GND
GND
4D1
4D2
P
4Q4
4Q3
VCC
VCC
4D3
4D4
R
4Q6
4Q5
GND
GND
4D5
4D6
T
4Q7
4Q8
4OE
4CLK
4D8
4D7
FUNCTION TABLE
(each flip-flop)
INPUTS
OE CLK D
OUTPUT
Q
L
H
H
L
L
L
L H or L X
Q0
H
X
X
Z
2
POST OFFICE BOX 655303 DALLAS, TEXAS 75265




 SN74AUCH32374
logic diagram (positive logic)
A3
1OE
A4
1CLK
C1
A5
1D1
1D
SN74AUCH32374
32-BIT EDGE-TRIGGERED D-TYPE FLIP-FLOP
WITH 3-STATE OUTPUTS
SCES476 – AUGUST 2003
H3
2OE
H4
2CLK
A2
C1
1Q1
E5
2D1
1D
E2
2Q1
J3
3OE
J4
3CLK
J5
3D1
To Seven Other Channels
C1
1D
T3
4OE
T4
4CLK
J2
3Q1
N5
4D1
To Seven Other Channels
C1
1D
N2
4Q1
To Seven Other Channels
To Seven Other Channels
absolute maximum ratings over operating free-air temperature range (unless otherwise noted)
Supply voltage range, VCC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.5 V to 3.6 V
Input voltage range, VI (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.5 V to 3.6 V
Voltage range applied to any output in the high-impedance or power-off state, VO
(see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.5 V to 3.6 V
Output voltage range, VO (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.5 V to VCC + 0.5 V
Input clamp current, IIK (VI < 0) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –50 mA
Output clamp current, IOK (VO < 0) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –50 mA
Continuous output current, IO . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ±20 mA
Continuous current through VCC or GND . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ±100 mA
Package thermal impedance, θJA (see Note 2) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40°C/W
Storage temperature range, Tstg . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –65°C to 150°C
Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and
functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not
implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
NOTES: 1. The input negative-voltage and output voltage ratings may be exceeded if the input and output current ratings are observed.
2. The package thermal impedance is calculated in accordance with JESD 51-7.
POST OFFICE BOX 655303 DALLAS, TEXAS 75265
3



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