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Integrated Hotswap. TPS25910 Datasheet

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Integrated Hotswap. TPS25910 Datasheet






TPS25910 Hotswap. Datasheet pdf. Equivalent




TPS25910 Hotswap. Datasheet pdf. Equivalent





Part

TPS25910

Description

20-V Integrated Hotswap



Feature


TPS25910 www.ti.com SLUSAR6D – SEPTE MBER 2012 – REVISED JANUARY 2014 6.5 -A, 20-V Integrated Hotswap with Progra mmable Inrush Slew Rate Check for Sampl es: TPS25910 FEATURES 1 • Up to 20-V Bus Operation • Integrated 30-mΩ P ass MOSFET • Programmable Current Lim it from: 0.83 A to 6.5 A • Programmab le Inrush Current Slew Rate • Thermal Shutdown and fault alert • 4-mm x.
Manufacture

Texas Instruments

Datasheet
Download TPS25910 Datasheet


Texas Instruments TPS25910

TPS25910; 4-mm QFN16 • –40°C to 125°C Junct ion Temperature Range • UL2367 Recogn ized - File Number E169910 • CB Certi fied APPLICATIONS • Solid State Drive (SSD) • Hard Disk Drive (HDD) • RA ID Arrays • Telecommunications • Pl ug-In Circuit Boards • Notebooks and Netbooks • PCIE • Fan Control DESC RIPTION The TPS25910 device provides hi ghly integrated hotswap power management and.


Texas Instruments TPS25910

superior protection in applications up to 20 V. The maximum UV turn-on thresho ld of 2.9 V makes the TPS25910 device w ell suited to standard bus voltages as low as 3.3 V. This device is intended f or systems where a voltage bus must be protected from undesired permanent and transient overload. At start-up or when hot plugging into the system bus, the TPS25910 device li.


Texas Instruments TPS25910

mits the inrush current by controlling t he ramp rate of the output voltage, VOU T. The slew rate of VOUT can be adjuste d with a capacitor between the GATE pin and the GND pin. Built in SOA protecti on ensures that the internal MOSFET ope rates inside a safe operating area (SOA ) under the harshest operating conditio ns. In addition, the current-limit thre shold, which is in.

Part

TPS25910

Description

20-V Integrated Hotswap



Feature


TPS25910 www.ti.com SLUSAR6D – SEPTE MBER 2012 – REVISED JANUARY 2014 6.5 -A, 20-V Integrated Hotswap with Progra mmable Inrush Slew Rate Check for Sampl es: TPS25910 FEATURES 1 • Up to 20-V Bus Operation • Integrated 30-mΩ P ass MOSFET • Programmable Current Lim it from: 0.83 A to 6.5 A • Programmab le Inrush Current Slew Rate • Thermal Shutdown and fault alert • 4-mm x.
Manufacture

Texas Instruments

Datasheet
Download TPS25910 Datasheet




 TPS25910
TPS25910
www.ti.com
SLUSAR6D – SEPTEMBER 2012 – REVISED JANUARY 2014
6.5-A, 20-V Integrated Hotswap with Programmable Inrush Slew Rate
Check for Samples: TPS25910
FEATURES
1
• Up to 20-V Bus Operation
• Integrated 30-mPass MOSFET
• Programmable Current Limit from:
0.83 A to 6.5 A
• Programmable Inrush Current Slew Rate
• Thermal Shutdown and fault alert
• 4-mm x 4-mm QFN16
• –40°C to 125°C Junction Temperature Range
• UL2367 Recognized - File Number E169910
• CB Certified
APPLICATIONS
• Solid State Drive (SSD)
• Hard Disk Drive (HDD)
• RAID Arrays
• Telecommunications
• Plug-In Circuit Boards
• Notebooks and Netbooks
• PCIE
• Fan Control
DESCRIPTION
The TPS25910 device provides highly integrated hot-
swap power management and superior protection in
applications up to 20 V. The maximum UV turn-on
threshold of 2.9 V makes the TPS25910 device well
suited to standard bus voltages as low as 3.3 V. This
device is intended for systems where a voltage bus
must be protected from undesired permanent and
transient overload.
At start-up or when hot plugging into the system bus,
the TPS25910 device limits the inrush current by
controlling the ramp rate of the output voltage, VOUT.
The slew rate of VOUT can be adjusted with a
capacitor between the GATE pin and the GND pin.
Built in SOA protection ensures that the internal
MOSFET operates inside a safe operating area
(SOA) under the harshest operating conditions. In
addition, the current-limit threshold, which is
independent of the power limit, can be adjusted with
a resistor between the ILIM pin and the GND pin.
The TPS25910 device provides a fault indicator
output when in thermal fault.
The TPS25910 device is available in a 16-pin QFN
package.
12-V, 4.75-A APPLICATION
Input
Voltage
Bus
1/2/3 IN
OUT 10/11 /12
16 EN
4 GATE
CEXT
GND
5/6
TPS25910
GND
8/9
ILIM GND
7
13
40.2 k?
FLT 15
CLOAD
GND
14
Optional: To
System
Monitor
Output To Voltage
Bus or DC -to-DC
Converter
1
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of the Texas
Instruments standard warranty. Production processing does not
necessarily include testing of all parameters.
Copyright © 2012–2014, Texas Instruments Incorporated




 TPS25910
TPS25910
SLUSAR6D – SEPTEMBER 2012 – REVISED JANUARY 2014
www.ti.com
These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam
during storage or handling to prevent electrostatic damage to the MOS gates.
ABSOLUTE MAXIMUM RATINGS
over device junction temperature range (unless otherwise noted)(1)(2)
Input voltage range IN, OUT
Voltage range, GATE
Voltage range FLT
Voltage ILIM
Output sink current FLT
Input voltage range, EN
Voltage range ILIM(3)
ESD rating
Human body model (HBM)
Charged device model (CDM)
Operating junction temperature range, TJ
Storage temperature range, Tstg
MIN
MAX
–0.3
22
–0.3
30
–0.3
20
1.75
10
–0.3
6
–0.3
3
2 .5
500
Internally Limited
–65
150
UNIT
V
V
mA
V
kV
V
°C
(1) Stresses beyond those listed under absolute maximum ratings may cause permanent damage to the device. These are stress ratings
only, and functional operation of the device at these or any other conditions beyond those indicated under recommended operating
conditions is not implied. Exposure to absolute–maximum–rated conditions for extended periods may affect device reliability.
(2) All voltage values are with respect to GND.
(3) Do not apply voltage to pin.
2
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Copyright © 2012–2014, Texas Instruments Incorporated




 TPS25910
TPS25910
www.ti.com
SLUSAR6D – SEPTEMBER 2012 – REVISED JANUARY 2014
RECOMMENDED OPERATING CONDITIONS
over device junction temperature range (unless otherwise noted)
PARAMETER
MIN
Input voltage range IN, OUT
3
Voltage range EN
0
Voltage range FLT
0
Continuous output current IOUT
0
Output sink current FLT
0
External Capacitor, GATE
1
dv/dt, VIN(1)
RLIM (2)
0
Junction temperature
–40
(1) dV/dt, VIN should be limited to 12 V/μS to confine the shoot-through current to the load.
(2) When RLIM value is beyond this range, ILIM will not be as accurate as within this range.
NOM
MAX
20
5
20
5
1
47
12
237k
125
UNIT
V
A
mA
nF
V/μS
Ω
°C
THERMAL INFORMATION
θJA
θJCtop
θJB
ψJT
ψJB
θJCbot
THERMAL METRIC(1)
Junction-to-ambient thermal resistance(2)
Junction-to-case (top) thermal resistance(3)
Junction-to-board thermal resistance(4)
Junction-to-top characterization parameter(5)
Junction-to-board characterization parameter(6)
Junction-to-case (bottom) thermal resistance(7)
TPS25910
RSA (QFN)
16 PINS
34.8
35.3
11.9
0.4
12.0
3.3
UNITS
°C/W
(1) For more information about traditional and new thermal metrics, see the IC Package Thermal Metrics application report, SPRA953.
(2) The junction-to-ambient thermal resistance under natural convection is obtained in a simulation on a JEDEC-standard, high-K board, as
specified in JESD51-7, in an environment described in JESD51-2a.
(3) The junction-to-case (top) thermal resistance is obtained by simulating a cold plate test on the package top. No specific JEDEC-
standard test exists, but a close description can be found in the ANSI SEMI standard G30-88.
(4) The junction-to-board thermal resistance is obtained by simulating in an environment with a ring cold plate fixture to control the PCB
temperature, as described in JESD51-8.
(5) The junction-to-top characterization parameter, ψJT, estimates the junction temperature of a device in a real system and is extracted
from the simulation data for obtaining θJA, using a procedure described in JESD51-2a (sections 6 and 7).
(6) The junction-to-board characterization parameter, ψJB, estimates the junction temperature of a device in a real system and is extracted
from the simulation data for obtaining θJA , using a procedure described in JESD51-2a (sections 6 and 7).
(7) The junction-to-case (bottom) thermal resistance is obtained by simulating a cold plate test on the exposed (power) pad. No specific
JEDEC standard test exists, but a close description can be found in the ANSI SEMI standard G30-88.
Spacer
Copyright © 2012–2014, Texas Instruments Incorporated
Product Folder Links: TPS25910
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