SNJ4HCT377FK

D Operating Voltage Range of 4.5 V to 5.5 V D Outputs Can Drive Up To 10 LSTTL Loads D Low Power Consumption, 80-µA Max ICC D Typical tpd = 12 ns D ±4-mA Output Drive at 5 V D Low Input Current of 1 µA Max D Inputs Are TTL-Voltage Compatible SN54HCT377 . . . J OR W PACKAGE SN74HCT377 . . . DW OR N PACKAGE (TOP VIEW) SN54HCT377, SN74HCT377 OCTAL D-TYPE FLIP-FLOPS WITH CLOCK ENABLE SCLS067D – NOVEMBER 1988 – REVISED MARCH 2003 D Contain Eight Flip-Flops With Single-Rail Outputs D Clock Enable Latched to Avoid False Clocking D Applications Include: – Buffer/Storage Registers – Shift Registers – Pattern Generators SN54HCT377 . . . FK PACKAGE (TOP VIEW) 1D 1Q CLKEN VCC 8Q CLKEN 1 1Q 2 1D 3 2D 4 2Q 5 3Q 6 3D 7 4D 8 4Q 9 GND 10 20 VCC 19 8Q 18 8D 17 7D 16 7Q 15 6Q 14 6D 13 5D 12 5Q 11 CLK 2D 3 2 1 20 19 4 18 8D 2Q 5 17 7D 3Q 6 16 7Q 3D 7 15 6Q 4D 8 14 6D 9 10 11 12 13 4Q GND CLK 5Q 5D description/ordering information These devices are positive-edge-triggered D-type flip-flops. The ’HCT377 devices are similar to the ’HCT273 devices, but feature a latched clock-enable (CLKEN) input instead of a common clear. Information at the data (D) inputs meeting the setup time requirements is transferred to the Q outputs on the positive-going edge of the clock (CLK) pulse if CLKEN is low. Clock triggering occurs at a particular voltage level and is not directly related to the transition time of the positive-going pulse. When CLK is at either the high or low level, the D input ...