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Power-Supply Sequencer/Monitor. UCD9090 Datasheet

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Power-Supply Sequencer/Monitor. UCD9090 Datasheet
















UCD9090 Sequencer/Monitor. Datasheet pdf. Equivalent













Part

UCD9090

Description

10-Channel Power-Supply Sequencer/Monitor



Feature


Product Folder Order Now Technical Doc uments Tools & Software Support & Com munity Reference Design UCD9090 SLVSA 30D – APRIL 2011 – REVISED MARCH 20 19 UCD9090 10-rail power supply sequenc er and monitor with ACPI support 1 Fea tures •1 Monitor and sequence 10 volt age rails – All rails sampled every 4 00 μs – 12-bit ADC with 2.5-V, 0.5% internal VREF – Sequence base.
Manufacture

Texas Instruments

Datasheet
Download UCD9090 Datasheet


Texas Instruments UCD9090

UCD9090; d on time, rail and pin dependencies – Four programmable undervoltage and ove rvoltage thresholds per monitor • Non volatile error and peak-value logging p er monitor (up to 30 fault detail entri es) • Closed-loop margining for 10 ra ils – Margin output adjusts rail volt age to match user-defined margin thresh olds • Programmable watchdog timer an d system reset • Flexible di.


Texas Instruments UCD9090

gital I/O configuration • Pin-selected rail states • Cascading multiple dev ices • Multi-phase PWM clock generato r – Clock frequencies from 15.259 kHz to 125 MHz – Capability to configure independent clock outputs for synchron izing switch-mode power supplies • JT AG and I2C/SMBus/PMBus™ interfaces 2 Applications • Industrial and ATE • Telecommunications and networking e.


Texas Instruments UCD9090

quipment • Servers and storage systems • Any system requiring sequencing an d monitoring of multiple power rails 3 Description The UCD9090 is a 10-rail PM Bus/I2C addressable power-supply sequen cer and monitor. The device integrates a 12-bit ADC for monitoring up to 10 po wer-supply voltage inputs. Twenty-three GPIO pins can be used for power supply enables, power-on res.





Part

UCD9090

Description

10-Channel Power-Supply Sequencer/Monitor



Feature


Product Folder Order Now Technical Doc uments Tools & Software Support & Com munity Reference Design UCD9090 SLVSA 30D – APRIL 2011 – REVISED MARCH 20 19 UCD9090 10-rail power supply sequenc er and monitor with ACPI support 1 Fea tures •1 Monitor and sequence 10 volt age rails – All rails sampled every 4 00 μs – 12-bit ADC with 2.5-V, 0.5% internal VREF – Sequence base.
Manufacture

Texas Instruments

Datasheet
Download UCD9090 Datasheet




 UCD9090
Product
Folder
Order
Now
Technical
Documents
Tools &
Software
Support &
Community
Reference
Design
UCD9090
SLVSA30D – APRIL 2011 – REVISED MARCH 2019
UCD9090 10-rail power supply sequencer and monitor with ACPI support
1 Features
1 Monitor and sequence 10 voltage rails
– All rails sampled every 400 μs
– 12-bit ADC with 2.5-V, 0.5% internal VREF
– Sequence based on time, rail and pin
dependencies
– Four programmable undervoltage and
overvoltage thresholds per monitor
• Nonvolatile error and peak-value logging per
monitor (up to 30 fault detail entries)
• Closed-loop margining for 10 rails
– Margin output adjusts rail voltage to match
user-defined margin thresholds
• Programmable watchdog timer and system reset
• Flexible digital I/O configuration
• Pin-selected rail states
• Cascading multiple devices
• Multi-phase PWM clock generator
– Clock frequencies from 15.259 kHz to
125 MHz
– Capability to configure independent clock
outputs for synchronizing switch-mode power
supplies
• JTAG and I2C/SMBus/PMBus™ interfaces
2 Applications
• Industrial and ATE
• Telecommunications and networking equipment
• Servers and storage systems
• Any system requiring sequencing and monitoring
of multiple power rails
3 Description
The UCD9090 is a 10-rail PMBus/I2C addressable
power-supply sequencer and monitor. The device
integrates a 12-bit ADC for monitoring up to 10
power-supply voltage inputs. Twenty-three GPIO pins
can be used for power supply enables, power-on
reset signals, external interrupts, cascading, or other
system functions. Ten of these pins offer PWM
functionality. Using these pins, the UCD9090 offers
support for margining, and general-purpose PWM
functions.
Specific power states can be achieved using the pin-
selected rail states feature. This feature allows with
the use of up to 3 GPIs to enable and disable any
rail. This is useful for implementing system low-power
modes and the Advanced Configuration and Power
Interface (ACPI) specification that is used for
hardware devices.
The TI Fusion Digital Power™ designer software
provides device configuration. This PC-based user
interface (UI) offers an intuitive interface for
configuring, storing, and monitoring all system
operating parameters.
Device Information(1)
PART NUMBER
PACKAGE
BODY SIZE (NOM)
UCD9090
VQFN (48)
7.00 mm × 7.00 mm
(1) For all available packages, see the orderable addendum at
the end of the data sheet.
VOUT 12 V
VIN 12 V
INA196
VOUT 12 V
VOUT 3.3 V
VOUT 1.8 V
VOUT 0.8 V
VIN 0.8
Temp 0.8 V
VIN 12 V
Temp 12 V
WDI from main
processor
WDO
POWER_GOOD
WARN_OV_ 0.8 V
or
WARN_OV_12 V
SYSTEM_RESET
Other
sequencer done
(cascade input)
Typical Application
3.3-V Supply
V33A V33D
12-V OUT
TEMP12V
Temp IC
VMON
GPIO
UCD9090
VMON
VMON
VMON
VMON
VMON
VMON
VMON
GPIO
GPIO
GPIO
GPIO
VIN
VOUT
EN
DC-DC1
VFB
VOUT
3.3 V
VIN
VOUT
EN
VOUT 1.8 V
LDO1
GPIO
TEMP0.8V
GPIO
GPIO
GPIO
VIN
VOUT
EN EN
DC-DC2
VFB
VOUT
0.8 V
I0.8V
INA196
I2C/PMBus
JTAG
2 MHz
PWM
VMARG
Closed loop margining
Copyright © 2016, Texas Instruments Incorporated
1
An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications,
intellectual property matters and other important disclaimers. PRODUCTION DATA.




 UCD9090
UCD9090
SLVSA30D – APRIL 2011 – REVISED MARCH 2019
www.ti.com
Table of Contents
1 Features .................................................................. 1
2 Applications ........................................................... 1
3 Description ............................................................. 1
4 Revision History..................................................... 2
5 Pin Configuration and Functions ......................... 4
6 Specifications......................................................... 6
6.1 Absolute Maximum Ratings ...................................... 6
6.2 ESD Ratings.............................................................. 6
6.3 Recommended Operating Conditions....................... 6
6.4 Thermal Information .................................................. 6
6.5 Electrical Characteristics........................................... 7
6.6 I2C/Smbus/PMBus Timing Requirements ................. 8
6.7 Typical Characteristics .............................................. 9
7 Detailed Description ............................................ 10
7.1 Overview ................................................................. 10
7.2 Functional Block Diagram ....................................... 10
7.3 Feature Description................................................. 11
7.4 Device Functional Modes........................................ 17
7.5 Programming........................................................... 37
8 Application and Implementation ........................ 41
8.1 Application Information............................................ 41
8.2 Typical Application ................................................. 42
9 Power Supply Recommendations...................... 45
10 Layout................................................................... 45
10.1 Layout Guidelines ................................................. 45
10.2 Layout Example .................................................... 46
11 Device and Documentation Support ................. 48
11.1 Documentation Support ........................................ 48
11.2 Receiving Notification of Documentation Updates 48
11.3 Community Resources.......................................... 48
11.4 Trademarks ........................................................... 48
11.5 Electrostatic Discharge Caution ............................ 48
11.6 Glossary ................................................................ 48
12 Mechanical, Packaging, and Orderable
Information ........................................................... 48
4 Revision History
NOTE: Page numbers for previous revisions may differ from page numbers in the current version.
Changes from Revision C (August 2016) to Revision D
Page
• Changed Bus free time between start and stop specifications minimum from "4.7 μs" to "1.3 μs" in
I2C/Smbus/PMBus Timing Requirements section ................................................................................................................. 8
• Changed Hold time after (repeated) start, Repeated-start setup time, Stop setup time, and Clock high period
specifications minimum from "0.26 μs" to "0.6 μs" in I2C/Smbus/PMBus Timing Requirements section............................... 8
• Changed Data setup time specification minimum from "50 ns" to "100 ns" in I2C/Smbus/PMBus Timing
Requirements section ............................................................................................................................................................. 8
• Changed Clock low period specification minimum from "0.5 μs" to "1.3 μs" in I2C/Smbus/PMBus Timing
Requirements section ............................................................................................................................................................. 8
• Changed Clock/data fall time specification maximum from "120 ns" to "300 ns" in I2C/Smbus/PMBus Timing
Requirements section ............................................................................................................................................................. 8
• Added Total capacitance of one bus line specification to I2C/Smbus/PMBus Timing Requirements section........................ 8
• Clarified instructions in Programming section ..................................................................................................................... 37
• Updated Table 10 ................................................................................................................................................................. 40
• Clarified Full Configuration Update While in Normal Mode section ..................................................................................... 40
• Added steps 6 through 9 in Design Requirements section .................................................................................................. 43
Changes from Revision B (December 2015) to Revision C
Page
• Added Cascading multiple devices feature to Features section............................................................................................. 1
• Updated Fault Responses and Alert Processing section ..................................................................................................... 22
• Added Cascading Multiple Devices section ........................................................................................................................ 28
• Updated Device Reset section ............................................................................................................................................. 36
• Added Receiving Notification of Documentation Updates section ...................................................................................... 48
2
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Product Folder Links: UCD9090
Copyright © 2011–2019, Texas Instruments Incorporated




 UCD9090
www.ti.com
UCD9090
SLVSA30D – APRIL 2011 – REVISED MARCH 2019
Changes from Revision A (August 2011) to Revision B
Page
• Added Pin Configuration and Functions section, ESD Ratings table, Feature Description section, Device Functional
Modes, Application and Implementation section, Power Supply Recommendations section, Layout section, Device
and Documentation Support section, and Mechanical, Packaging, and Orderable Information section ............................... 1
• Changed minimum storage temperature from –40 to –55...................................................................................................... 6
• Changed the Functional Block Diagram ............................................................................................................................... 10
• Deleted the second paragraph under Monitoring section..................................................................................................... 19
• Updated Voltage Monitoring section..................................................................................................................................... 19
• Updated pin numbers in GPIO Pin Configuration Options table. ......................................................................................... 25
• Updated first item in the GPI Special Functions section. ..................................................................................................... 28
• Updated last sentence in Power-Supply Enables section. ................................................................................................... 28
• Updated JTAG INTERFACE section. ................................................................................................................................... 37
• Updated Programming section. ............................................................................................................................................ 39
Copyright © 2011–2019, Texas Instruments Incorporated
Product Folder Links: UCD9090
Submit Documentation Feedback
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