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Power-Supply Sequencer/Monitor. UCD90120A Datasheet

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Power-Supply Sequencer/Monitor. UCD90120A Datasheet
















UCD90120A Sequencer/Monitor. Datasheet pdf. Equivalent













Part

UCD90120A

Description

12-Rail Power-Supply Sequencer/Monitor



Feature


Product Folder Order Now Technical Doc uments Tools & Software Support & Com munity Reference Design UCD90120A SLV SAN9C – APRIL 2011 – REVISED MARCH 2019 UCD90120A 12-Rail Power Supply Seq uencer and Monitor With ACPI Support 1 Features •1 Monitor and Sequence 12 Voltage Rails – All Rails Sampled Eve ry 400 μs – 12-bit ADC With 2.5-V, 0 .5% Internal VREF – Sequence .
Manufacture

Texas Instruments

Datasheet
Download UCD90120A Datasheet


Texas Instruments UCD90120A

UCD90120A; Based on Time, Rail and Pin Dependencies – Four Programmable Undervoltage and Overvoltage Thresholds per Monitor • Nonvolatile Error and Peak-Value Loggi ng per Monitor (up to 12 Fault Detail E ntries) • Closed-Loop Margining for 1 0 Rails – Margin Output Adjusts Rail Voltage to Match User-Defined Margin Th resholds • Programmable Watchdog Time r and System Reset • Flexibl.


Texas Instruments UCD90120A

e Digital I/O Configuration • Pin-Sele cted Rail States • Multiphase PWM Clo ck Generator – Clock Frequencies From 15.259 kHz to 125 MHz – Capability t o Configure Independent Clock Outputs f or Synchronizing Switch-Mode Power Supp lies • JTAG and I2C/SMBus/PMBus™ In terfaces 2 Applications • Industrial / ATE • Telecommunications and Networ king Equipment • Servers and Stora.


Texas Instruments UCD90120A

ge Systems • Any System Requiring Sequ encing and Monitoring of Multiple Power Rails 3 Description The UCD90120A is a 12-rail PMBus/I2C addressable power-su pply sequencer and monitor. The device integrates a 12-bit ADC for monitoring up to 12 power-supply voltage inputs. T wenty-six GPIO pins can be used for pow er supply enables, power-on reset signa ls, external interru.





Part

UCD90120A

Description

12-Rail Power-Supply Sequencer/Monitor



Feature


Product Folder Order Now Technical Doc uments Tools & Software Support & Com munity Reference Design UCD90120A SLV SAN9C – APRIL 2011 – REVISED MARCH 2019 UCD90120A 12-Rail Power Supply Seq uencer and Monitor With ACPI Support 1 Features •1 Monitor and Sequence 12 Voltage Rails – All Rails Sampled Eve ry 400 μs – 12-bit ADC With 2.5-V, 0 .5% Internal VREF – Sequence .
Manufacture

Texas Instruments

Datasheet
Download UCD90120A Datasheet




 UCD90120A
Product
Folder
Order
Now
Technical
Documents
Tools &
Software
Support &
Community
Reference
Design
UCD90120A
SLVSAN9C – APRIL 2011 – REVISED MARCH 2019
UCD90120A 12-Rail Power Supply Sequencer and Monitor With ACPI Support
1 Features
1 Monitor and Sequence 12 Voltage Rails
– All Rails Sampled Every 400 μs
– 12-bit ADC With 2.5-V, 0.5% Internal VREF
– Sequence Based on Time, Rail and Pin
Dependencies
– Four Programmable Undervoltage and
Overvoltage Thresholds per Monitor
• Nonvolatile Error and Peak-Value Logging per
Monitor (up to 12 Fault Detail Entries)
• Closed-Loop Margining for 10 Rails
– Margin Output Adjusts Rail Voltage to Match
User-Defined Margin Thresholds
• Programmable Watchdog Timer and System
Reset
• Flexible Digital I/O Configuration
• Pin-Selected Rail States
• Multiphase PWM Clock Generator
– Clock Frequencies From 15.259 kHz to
125 MHz
– Capability to Configure Independent Clock
Outputs for Synchronizing Switch-Mode Power
Supplies
• JTAG and I2C/SMBus/PMBus™ Interfaces
2 Applications
• Industrial / ATE
• Telecommunications and Networking Equipment
• Servers and Storage Systems
• Any System Requiring Sequencing and Monitoring
of Multiple Power Rails
3 Description
The UCD90120A is a 12-rail PMBus/I2C addressable
power-supply sequencer and monitor. The device
integrates a 12-bit ADC for monitoring up to 12
power-supply voltage inputs. Twenty-six GPIO pins
can be used for power supply enables, power-on
reset signals, external interrupts, cascading, or other
system functions. Twelve of these pins offer PWM
functionality. Using these pins, the UCD90120A offers
support for margining, and general-purpose PWM
functions.
Specific power states can be achieved using the Pin-
Selected Rail States feature. This feature allows with
the use of up to 3 GPIs to enable and disable any
rail. This is useful for implementing system low-power
modes and the Advanced Configuration and Power
Interface (ACPI) specification that is used for
hardware devices.
The TI Fusion Digital Power™ designer software is
provided for device configuration. This PC-based
graphical user interface (GUI) offers an intuitive
interface for configuring, storing, and monitoring all
system operating parameters.
Device Information(1)
PART NUMBER
PACKAGE
BODY SIZE (NOM)
UCD90120A
VQFN (64)
9.00 mm × 9.00 mm
(1) For all available packages, see the orderable addendum at
the end of the data sheet.
12V
I12V
INA196
Simplified Schematic
3.3V
Supply
12V OUT
TEMP12V
TEMP IC
12V OUT
3.3V OUT
1.8V OUT
0.8V OUT
I0.8V
TEMP0.8V
I12V
TEMP12V
WDI from main
processor
WDO
POWER_GOOD
WARN_OC_0.8V_
OR_12V
SYSTEM RESET
OTHER
SEQUENCER DONE
(CASCADE INPUT)
VMON
VMON
VMON
VMON
VMON
VMON
VMON
VMON
GPIO
GPIO
GPIO
GPIO
GPIO
GPIO
UCD90120A
I2C/
PMBUS
GPIO
GPIO
GPIO
GPIO
2MHz
PWM
VIN
VOUT
/EN
DC-DC 1
VFB
3.3V OUT
VIN
/EN VOUT
LDO1
1.8V OUT
TEMP0.8V
TEMP IC
VIN
VOUT
/EN
DC-DC 2
VFB
0.8V OUT
I0.8V
INA196
Vmarg
Closed Loop
Margining
JTAG
1
An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications,
intellectual property matters and other important disclaimers. PRODUCTION DATA.




 UCD90120A
UCD90120A
SLVSAN9C – APRIL 2011 – REVISED MARCH 2019
www.ti.com
Table of Contents
1 Features .................................................................. 1
2 Applications ........................................................... 1
3 Description ............................................................. 1
4 Revision History..................................................... 2
5 Pin Configuration and Functions ......................... 3
6 Specifications......................................................... 6
6.1 Absolute Maximum Ratings ...................................... 6
6.2 ESD Ratings ............................................................ 7
6.3 Recommended Operating Conditions....................... 7
6.4 Thermal Information .................................................. 7
6.5 Electrical Characteristics........................................... 7
6.6 I2C/SMBus/PMBus Timing Requirements................. 8
6.7 Typical Characteristics ............................................ 10
7 Detailed Description ............................................ 11
7.1 Overview ................................................................. 11
7.2 Functional Block Diagram ....................................... 11
7.3 Feature Description................................................. 12
7.4 Device Functional Modes........................................ 18
7.5 Programming .......................................................... 39
8 Application and Implementation ........................ 44
8.1 Application Information............................................ 44
8.2 Typical Application ................................................. 45
9 Power Supply Recommendations...................... 48
10 Layout................................................................... 48
10.1 Layout Guidelines ................................................. 48
10.2 Layout Example .................................................... 48
11 Device and Documentation Support ................. 50
11.1 Documentation Support ....................................... 50
11.2 Community Resources.......................................... 50
11.3 Trademarks ........................................................... 50
11.4 Electrostatic Discharge Caution ............................ 50
11.5 Glossary ................................................................ 50
12 Mechanical, Packaging, and Orderable
Information ........................................................... 50
4 Revision History
NOTE: Page numbers for previous revisions may differ from page numbers in the current version.
Changes from Revision B (December 2015) to Revision C
Page
• Clarified instructions in Device Configuration and Programming section ............................................................................ 39
• Added steps 6 through 9 in Design Requirements section .................................................................................................. 46
Changes from Revision A (October 2015) to Revision B
Page
• Updated Voltage Monitoring section for clarification. ........................................................................................................... 20
Changes from Original (April 2011 ) to Revision A
Page
• Added ESD Ratings table, Feature Description section, Device Functional Modes, Application and Implementation
section, Power Supply Recommendations section, Layout section, Device and Documentation Support section, and
Mechanical, Packaging, and Orderable Information section .................................................................................................. 1
• Added Monitoring section with Votage Monitoring as a subordinate section. ...................................................................... 20
• Changed Updated Voltage Monitoring section ..................................................................................................................... 20
• Deleted the end of second paragraph in Voltage Monitoring section that read "'and 62.2....analog inputs". ...................... 20
• Added Current Monitoring section with Remote Temperature Monitoring And Internal Temperature Sensor as
subsections........................................................................................................................................................................... 21
• Changed the first sentence of Fault Responses....Processing section ................................................................................ 23
• Added Run Time Clock section ............................................................................................................................................ 36
• Changed 'CAUTION' to 'NOTE' and added new first paragraph.......................................................................................... 39
• Changed second sentence in paragraph under Figure 31 from "For small runs,...GUI". to "For small runs....for this
purpose"................................................................................................................................................................................ 41
• Added new paragraph in JTAG Interface section................................................................................................................. 43
2
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Copyright © 2011–2019, Texas Instruments Incorporated




 UCD90120A
www.ti.com
5 Pin Configuration and Functions
UCD90120A
SLVSAN9C – APRIL 2011 – REVISED MARCH 2019
NOTE
The maximum number of configurable rails is 12. The maximum number of configurable
GPIs is 8. The maximum number of configurable Boolean Logic GPOs is 12.
RGC Package
64-Pin VQFN
Top View
MON1 1
MON2 2
MON3 3
MON4 4
MON5 5
MON6 6
V33DIO1 7
DVSS1 8
RESET 9
TRCK 10
GPIO1 11
GPIO2 12
GPIO3 13
GPIO4 14
PMBUS_CLK 15
PMBUS_DATA 16
UCD90120A
48 AVSS2
47 BPCAP
46 V33A
45 V33D
44 V33DIO2
43 DVSS3
42 PWM3/GPI3
41 PWM4/GPI4
40 TRST
39 TMS/GPIO22
38 TDI/GPIO21
37 TDO/GPIO20
36 TCK/GPIO19
35 GPIO18
34 GPIO17
33 GPIO16
Copyright © 2011–2019, Texas Instruments Incorporated
Product Folder Links: UCD90120A
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