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CMOS SyncFIFO. IDT72V215 Datasheet

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CMOS SyncFIFO. IDT72V215 Datasheet
















IDT72V215 SyncFIFO. Datasheet pdf. Equivalent













Part

IDT72V215

Description

3.3 VOLT CMOS SyncFIFO



Feature


3.3 VOLT CMOS SyncFIFOTM IDT72V205, IDT 72V215, 256 x 18, 512 x 18, 1,024 x 18 , IDT72V225, IDT72V235, 2,048 x 18, a nd 4,096 x 18 IDT72V245 LEAD FINISH ( SnPb) ARE IN EOL PROCESS - LAST TIME BU Y EXPIRES JUNE 15, 2018 FEATURES: • 256 x 18-bit organization array (IDT72V 205) • 512 x 18-bit organization arra y (IDT72V215) • 1,024 x 18-bit organi zation array (IDT72V225).
Manufacture

Renesas

Datasheet
Download IDT72V215 Datasheet


Renesas IDT72V215

IDT72V215; • 2,048 x 18-bit organization array ( IDT72V235) • 4,096 x 18-bit organizat ion array (IDT72V245) • 10 ns read/wr ite cycle time • 5V input tolerant IDT Standard or First Word Fall Throu gh timing • Single or double register -buffered Empty and Full flags • Easi ly expandable in depth and width • As ynchronous or coincident Read and Write Clocks • Asynchronous or synchron.


Renesas IDT72V215

ous programmable Almost-Empty and Almost -Full flags with default settings • H alf-Full flag capability • Output ena ble puts output data bus in high-impeda nce state • High-performance submicro n CMOS technology • Available in a 64 -lead thin quad flatpack (TQFP/STQFP) • Industrial temperature range (–40 °C to +85°C) is available • Green p arts available, see ordering infor.


Renesas IDT72V215

mation DESCRIPTION: The IDT72V205/72V215 /72V225/72V235/72V245 are functionally compatible versions of the IDT72205LB/7 2215LB/72225LB/72235LB/72245LB, designe d to run off a 3.3V supply for exceptio nally low power consumption. These devi ces are very high-speed, low-power Firs t-In, First-Out (FIFO) memories with cl ocked read and write controls. These FI FOs are applicable.





Part

IDT72V215

Description

3.3 VOLT CMOS SyncFIFO



Feature


3.3 VOLT CMOS SyncFIFOTM IDT72V205, IDT 72V215, 256 x 18, 512 x 18, 1,024 x 18 , IDT72V225, IDT72V235, 2,048 x 18, a nd 4,096 x 18 IDT72V245 LEAD FINISH ( SnPb) ARE IN EOL PROCESS - LAST TIME BU Y EXPIRES JUNE 15, 2018 FEATURES: • 256 x 18-bit organization array (IDT72V 205) • 512 x 18-bit organization arra y (IDT72V215) • 1,024 x 18-bit organi zation array (IDT72V225).
Manufacture

Renesas

Datasheet
Download IDT72V215 Datasheet




 IDT72V215
3.3 VOLT CMOS SyncFIFOTM
IDT72V205, IDT72V215,
256 x 18, 512 x 18, 1,024 x 18,
IDT72V225, IDT72V235,
2,048 x 18, and 4,096 x 18
IDT72V245
LEAD FINISH (SnPb) ARE IN EOL PROCESS - LAST TIME BUY EXPIRES JUNE 15, 2018
FEATURES:
256 x 18-bit organization array (IDT72V205)
512 x 18-bit organization array (IDT72V215)
1,024 x 18-bit organization array (IDT72V225)
2,048 x 18-bit organization array (IDT72V235)
4,096 x 18-bit organization array (IDT72V245)
10 ns read/write cycle time
5V input tolerant
IDT Standard or First Word Fall Through timing
Single or double register-buffered Empty and Full flags
Easily expandable in depth and width
Asynchronous or coincident Read and Write Clocks
Asynchronous or synchronous programmable Almost-Empty
and Almost-Full flags with default settings
Half-Full flag capability
Output enable puts output data bus in high-impedance state
High-performance submicron CMOS technology
Available in a 64-lead thin quad flatpack (TQFP/STQFP)
Industrial temperature range (–40°C to +85°C) is available
Green parts available, see ordering information
DESCRIPTION:
The IDT72V205/72V215/72V225/72V235/72V245 are functionally com-
patible versions of the IDT72205LB/72215LB/72225LB/72235LB/72245LB,
designed to run off a 3.3V supply for exceptionally low power consumption.
These devices are very high-speed, low-power First-In, First-Out (FIFO)
memories with clocked read and write controls. These FIFOs are applicable
for a wide variety of data buffering needs, such as optical disk controllers, Local
Area Networks (LANs), and interprocessor communication.
These FIFOs have 18-bit input and output ports. The input port is controlled
by a free-running clock (WCLK), and an input enable pin (WEN). Data is read
into the synchronous FIFO on every clock when WEN is asserted. The output
port is controlled by another clock pin (RCLK) and another enable pin (REN).
The Read Clock(RCLK) can be tied to the Write Clock for single clock operation
or the two clocks can run asynchronous of one another for dual-clock operation.
An Output Enable pin (OE) is provided on the read port for three-state control
of the output.
FUNCTIONAL BLOCK DIAGRAM
WEN WCLK
FL
WXI
(HF)/WXO
RXI
RXO
RS
WRITE CONTROL
LOGIC
WRITE POINTER
EXPANSION LOGIC
RESET LOGIC
D0-D17
INPUT REGISTER
RAM ARRAY
256 x 18, 512 x 18
1,024 x 18, 2,048 x 18
4,096 x 18
OUTPUT REGISTER
OE
Q0-Q17
LD
OFFSET REGISTER
FLAG
LOGIC
READ POINTER
READ CONTROL
LOGIC
FF/IR
PAF
EF/OR
PAE
HF/(WXO)
RCLK REN
4294 drw 01
IDT, IDT logo are registered trademarks of Integrated Device Technology, Inc. SyncFIFO is a trademark of Integrated Device Technology, Inc.
COMMERCIAL AND INDUSTRIAL TEMPERATURE RANGES
1
©2018 Integrated Device Technology, Inc. All rights reserved. Product specifications subject to change without notice.
MARCH 2018
DSC-4294/8




 IDT72V215
IDT72V205/72V215/72V225/72V235/72V245 3.3V CMOS SyncFIFOTM
256 x 18, 512 x 18, 1,024 x 18, 2,048 x 18 and 4,096 x 18
COMMERCIAL AND INDUSTRIAL
TEMPERATURE RANGES
DESCRIPTION (CONTINUED)
The synchronous FIFOs have two fixed flags, Empty Flag/Output Ready
(EF/OR) and Full Flag/Input Ready (FF/IR), and two programmable flags,
Almost-Empty (PAE) and Almost-Full (PAF). The offset loading of the
programmable flags is controlled by a simple state machine, and is initiated by
asserting the Load pin (LD). A Half-Full flag (HF) is available when the FIFO
is used in a single device configuration.
There are two possible timing modes of operation with these devices: IDT
Standard mode and First Word Fall-Through (FWFT) mode.
In IDT Standard Mode, the first word written to an empty FIFO will not appear
on the data output lines unless a specific read operation is performed. A read
operation, which consists of activating REN and enabling a rising RCLK edge,
will shift the word from internal memory to the data output lines.
In FWFT mode, the first word written to an empty FIFO is clocked directly
to the data output lines after three transitions of the RCLK signal. A REN does
not have to be asserted for accessing the first word.
These devices are depth expandable using a Daisy-Chain technique or
First Word Fall Through mode (FWFT). The XI and XO pins are used to expand
the FIFOs. In depth expansion configuration, First Load (FL) is grounded on
the first device and set to HIGH for all other devices in the Daisy Chain.
The IDT72V205/72V215/72V225/72V235/72V245 are fabricated using
high-speed submicron CMOS technology.
PIN CONFIGURATIONS
PIN 1
D15
1
D14
2
D13
3
D12
4
D11
5
D10
6
D9
7
D8
8
D7
9
D6
10
D5
11
D4
12
D3
13
D2
14
D1
15
D0
16
48
Q14
47
Q13
46
GND
45
Q12
44
Q11
43
VCC
42
Q10
41
Q9
40
GND
39
Q8
38
Q7
37
Q6
36
Q5
35
GND
34
Q4
33
VCC
TQFP (PN64-1, order code: PF)
STQFP (PP64-1, order code: TF)
TOP VIEW
4294 drw 02
2




 IDT72V215
IDT72V205/72V215/72V225/72V235/72V245 3.3V CMOS SyncFIFOTM
256 x 18, 512 x 18, 1,024 x 18, 2,048 x 18 and 4,096 x 18
COMMERCIAL AND INDUSTRIAL
TEMPERATURE RANGES
PIN DESCRIPTION
Symbol
Name
D0–D17 DataInputs
RS
Reset
WCLK
WEN
Write Clock
Write Enable
RCLK
REN
Read Clock
Read Enable
OE
Output Enable
LD
Load
FL
First Load
WXI
Write Expansion
Input
RXI
Read Expansion
Input
FF/IR
Full Flag/
Input Ready
EF/OR
PAE
Empty Flag/
Output Ready
Programmable
Almost-Empty Flag
PAF
WXO/HF
Programmable
Almost-Full Flag
Write Expansion
Out/Half-Full Flag
RXO
Q0–Q17
VCC
GND
Read Expansion
Out
Data Outputs
Power
Ground
I/O
Description
I Data inputs for an 18-bit bus.
I When RS is set LOW, internal read and write pointers are set to the first location of the RAM array, FF and PAF
go HIGH, and PAE and EF go LOW. A reset is required before an initial WRITE after power-up.
I When WEN is LOW, data is written into the FIFO on a LOW-to-HIGH transition of WCLK, if the FIFO is not full.
I When WEN is LOW, data is written into the FIFO on every LOW-to-HIGH transition of WCLK. When WEN is
HIGH, the FIFO holds the previous data. Data will not be written into the FIFO if the FF is LOW.
I When REN is LOW, data is read from the FIFO on a LOW-to-HIGH transition of RCLK, if the FIFO is not empty.
I WhenRENisLOW,dataisreadfromtheFIFOoneveryLOW-to-HIGHtransitionofRCLK. WhenRENisHIGH,
the output register holds the previous data. Data will not be read from the FIFO if the EF is LOW.
I When OE is LOW, the data output bus is active. If OE is HIGH, the output data bus will be in a high-impedance
state.
I When LD is LOW, data on the inputs D0–D11 is written to the offset and depth registers on the LOW-to-HIGH
transition of the WCLK, when WEN is LOW. When LD is LOW, data on the outputs Q0–Q11 is read from the
offset and depth registers on the LOW-to-HIGH transition of the RCLK, when REN is LOW.
I In the single device or width expansion configuration, FL together with WXI and RXI determine if the mode is
IDT Standard mode or First Word Fall Through (FWFT) mode, as well as whether the PAE/PAF flags are
synchronous or asynchronous. (See Table 1.) In the Daisy Chain Depth Expansion configuration, FL is
grounded on the first device (first load device) and set to HIGH for all other devices in the Daisy Chain.
I In the single device or width expansion configuration, WXI together with FL and RXI determine if the mode
is IDT Standard mode or FWFT mode, as well as whether the PAE/PAF flags are synchronous or asynchronous.
(See Table 1.) In the Daisy Chain Depth Expansion configuration, WXI is connected to WXO (Write Expansion
Out) of the previous device.
I In the single device or width expansion configuration, RXI together with FL and WXI, determine if the mode
is IDT Standard mode or FWFT mode, as well as whether the PAE/PAF flags are synchronous or asynchronous.
(See Table 1.) In the Daisy Chain Depth Expansion configuration, RXI is connected to RXO (Read Expansion
Out) of the previous device.
O In the IDT Standard mode, the FF function is selected. FF indicates whether or not the FIFO memory is full. In
the FWFT mode, the IR function is selected. IR indicates whether or not there is space available for writing to
the FIFO memory.
O In the IDT Standard mode, the EF function is selected. EF indicates whether or not the FIFO memory is empty.
In FWFT mode, the OR function is selected. OR indicates whether or not there is valid data available at the outputs.
O When PAE is LOW, the FIFO is almost-empty based on the offset programmed into the FIFO. The default
offset at reset is 31 from empty for IDT72V205, 63 from empty for IDT72V215, and 127 from empty for IDT72V225/
72V235/72V245.
O When PAF is LOW, the FIFO is almost-full based on the offset programmed into the FIFO. The default offset at
reset is 31 from full for IDT72V205, 63 from full for IDT72V215, and 127 from full for IDT72V225/72V235/72V245.
O In the single device or width expansion configuration, the device is more than half full when HF is LOW. In the
depth expansion configuration, a pulse is sent from WXO to WXI of the next device when the last location in the
FIFO is written.
O In the depth expansion configuration, a pulse is sent from RXO to RXI of the next device when the last
location in the FIFO is read.
O Data outputs for an 18-bit bus.
+3.3V power supply pins.
Seven ground pins.
3




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