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Monostable Multivibrators. CD74HC423M Datasheet

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Monostable Multivibrators. CD74HC423M Datasheet
















CD74HC423M Multivibrators. Datasheet pdf. Equivalent













Part

CD74HC423M

Description

Dual Retriggerable Monostable Multivibrators



Feature


Data sheet acquired from Harris Semicond uctor SCHS142F September 1997 - Revised October 2003 CD54/74HC123, CD54/74HCT 123, CD74HC423, CD74HCT423 High-Speed C MOS Logic Dual Retriggerable Monostable Multivibrators with Resets [ /Title ( CD74 HC123 , CD74 HCT12 3, CD74 HC423 , CD74 HCT42 3) /Subject (High Speed Fe atures • Overriding Reset Terminates Output Pulse • Trigg.
Manufacture

Texas Instruments

Datasheet
Download CD74HC423M Datasheet


Texas Instruments CD74HC423M

CD74HC423M; ering From the Leading or Trailing Edge • Q and Q Buffered Outputs • Separa te Resets • Wide Range of Output-Puls e Widths • Schmitt Trigger on Both A and B Inputs • Fanout (Over Temperatu re Range) - Standard Outputs . . . . . . . . . . . . . . . 10 LSTTL Loads - Bu s Driver Outputs . . . . . . . . . . . . . 15 LSTTL Loads • Wide Operating T emperature Range . . . -55oC t.


Texas Instruments CD74HC423M

o 125oC • Balanced Propagation Delay a nd Transition Times • Significant Po wer Reduction Compared to LSTTL Logic I Cs • HC Types - 2V to 6V Operation - High Noise Immunity: NIL = 30%, NIH = 3 0%of VCC at VCC = 5V • HCT Types - 4. 5V to 5.5V Operation - Direct LSTTL Inp ut Logic Compatibility, VIL= 0.8V (Max) , VIH = 2V (Min) - CMOS Input Compatibi lity, Il ≤ 1µA at VOL, VOH D.


Texas Instruments CD74HC423M

escription The ’HC123, ’HCT123, CD74 HC423 and CD74HCT423 are dual monostabl e multivibrators with resets. They are all retriggerable and differ only in th at the 123 types can be triggered by a negative to positive reset pulse; where as the 423 types do not have this featu re. An external resistor (RX) and an ex ternal capacitor (CX) control the timin g and the accuracy for.





Part

CD74HC423M

Description

Dual Retriggerable Monostable Multivibrators



Feature


Data sheet acquired from Harris Semicond uctor SCHS142F September 1997 - Revised October 2003 CD54/74HC123, CD54/74HCT 123, CD74HC423, CD74HCT423 High-Speed C MOS Logic Dual Retriggerable Monostable Multivibrators with Resets [ /Title ( CD74 HC123 , CD74 HCT12 3, CD74 HC423 , CD74 HCT42 3) /Subject (High Speed Fe atures • Overriding Reset Terminates Output Pulse • Trigg.
Manufacture

Texas Instruments

Datasheet
Download CD74HC423M Datasheet




 CD74HC423M
Data sheet acquired from Harris Semiconductor
SCHS142F
September 1997 - Revised October 2003
CD54/74HC123, CD54/74HCT123,
CD74HC423, CD74HCT423
High-Speed CMOS Logic Dual Retriggerable
Monostable Multivibrators with Resets
[ /Title
(CD74
HC123
,
CD74
HCT12
3,
CD74
HC423
,
CD74
HCT42
3)
/Sub-
ject
(High
Speed
Features
• Overriding Reset Terminates Output Pulse
• Triggering From the Leading or Trailing Edge
• Q and Q Buffered Outputs
• Separate Resets
• Wide Range of Output-Pulse Widths
• Schmitt Trigger on Both A and B Inputs
• Fanout (Over Temperature Range)
- Standard Outputs . . . . . . . . . . . . . . . 10 LSTTL Loads
- Bus Driver Outputs . . . . . . . . . . . . . 15 LSTTL Loads
• Wide Operating Temperature Range . . . -55oC to 125oC
• Balanced Propagation Delay and Transition Times
• Significant Power Reduction Compared to LSTTL
Logic ICs
• HC Types
- 2V to 6V Operation
- High Noise Immunity: NIL = 30%, NIH = 30%of VCC at
VCC = 5V
• HCT Types
- 4.5V to 5.5V Operation
- Direct LSTTL Input Logic Compatibility,
VIL= 0.8V (Max), VIH = 2V (Min)
- CMOS Input Compatibility, Il 1µA at VOL, VOH
Description
The ’HC123, ’HCT123, CD74HC423 and CD74HCT423 are
dual monostable multivibrators with resets. They are all
retriggerable and differ only in that the 123 types can be
triggered by a negative to positive reset pulse; whereas the
423 types do not have this feature. An external resistor (RX)
and an external capacitor (CX) control the timing and the
accuracy for the circuit. Adjustment of Rx and CX provides a
wide range of output pulse widths from the Q and Q
terminals. Pulse triggering on the A and B inputs occur at a
particular voltage level and is not related to the rise and fall
times of the trigger pulses.
Once triggered, the output pulse width may be extended by
retriggering inputs A and B. The output pulse can be
terminated by a LOW level on the Reset (R) pin. Trailing
edge triggering (A) and leading edge triggering (B) inputs
are provided for triggering from either edge of the input
pulse. If either Mono is not used each input on the unused
device (A, B, and R) must be terminated high or low.
The minimum value of external resistance, Rx is typically
5k. The minimum value external capacitance, CX, is 0pF.
The calculation for the pulse width is tW = 0.45 RXCX at
VCC = 5V.
Ordering Information
PART NUMBER TEMP. RANGE (oC)
PACKAGE
CD54HC123F3A
-55 to 125
16 Ld CERDIP
CD54HCT123F3A
-55 to 125
16 Ld CERDIP
CD74HC123E
-55 to 125
16 Ld PDIP
CD74HC123M
-55 to 125
16 Ld SOIC
CD74HC123MT
-55 to 125
16 Ld SOIC
CD74HC123M96
-55 to 125
16 Ld SOIC
CD74HC123NSR
-55 to 125
16 Ld SOP
CD74HC123PW
-55 to 125
16 Ld TSSOP
CD74HC123PWR
-55 to 125
16 Ld TSSOP
CD74HC123PWT
-55 to 125
16 Ld TSSOP
CD74HC423E
-55 to 125
16 Ld PDIP
CD74HC423M
-55 to 125
16 Ld SOIC
CD74HC423MT
-55 to 125
16 Ld SOIC
CD74HC423M96
-55 to 125
16 Ld SOIC
CD74HC423NSR
-55 to 125
16 Ld SOP
CD74HCT123E
-55 to 125
16 Ld PDIP
CD74HCT123M
-55 to 125
16 Ld SOIC
CD74HCT123MT
-55 to 125
16 Ld SOIC
CD74HCT123M96
-55 to 125
16 Ld SOIC
CD74HCT423E
-55 to 125
16 Ld PDIP
CD74HCT423MT
-55 to 125
16 Ld SOIC
CD74HCT423M96
-55 to 125
16 Ld SOIC
NOTE: When ordering, use the entire part number. The suffixes 96
and R denote tape and reel. The suffix T denotes a small-quantity
reel of 250.
CAUTION: These devices are sensitive to electrostatic discharge. Users should follow proper IC Handling Procedures.
Copyright © 2003, Texas Instruments Incorporated
1




 CD74HC423M
Pinout
CD54/74HC123, CD54/74HCT123, CD74HC423, CD74HCT423
CD54HC123, CD54HCT123
(CERDIP)
CD74HC123
(PDIP, SOIC, SOP, TSSOP)
CD74HC423
(PDIP, SOIC, SOP)
CD74HCT123, CD74HCT423
(PDIP, SOIC)
TOP VIEW
1A 1
1B 2
1R 3
1Q 4
2Q 5
2CX 6
2RXCX 7
GND 8
16 VCC
15 1RXCX
14 1CX
13 1Q
12 2Q
11 2R
10 2B
9 2A
Functional Diagram
1A
1
1B
2
1R
3
11
2R
9
2A
10
2B
1Cx 1Rx
14
15
VCC
1Cx
1RxCx
13
1Q
MONO 1
4
1Q
MONO 2
5
2Q
12
2Q
2Cx
2RxCx
6
7
2Cx 2Rx
VCC
TRUTH TABLE
INPUTS
A
B
R
CD74HC/HCT123
H
X
H
X
L
H
L
H
OUTPUTS
Q
Q
L
H
L
H
H
H
X
X
L
L
H
L
H
CD74HC/HCT423
H
X
H
L
H
X
L
H
L
H
L
H
H
H
X
X
L
L
H
H = High Voltage Level, L = Low Voltage Level,
X = Don’t Care.
2




 CD74HC423M
CD54/74HC123, CD54/74HCT123, CD74HC423, CD74HCT423
Absolute Maximum Ratings
Thermal Information
DC Supply Voltage, VCC . . . . . . . . . . . . . . . . . . . . . . . . -0.5V to 7V
DC Input Diode Current, IIK
For VI < -0.5V or VI > VCC + 0.5V . . . . . . . . . . . . . . . . . . . . . .±20mA
DC Output Diode Current, IOK
For VO < -0.5V or VO > VCC + 0.5V . . . . . . . . . . . . . . . . . . . .±20mA
DC Output Source or Sink Current per Output Pin, IO
For VO > -0.5V or VO < VCC + 0.5V . . . . . . . . . . . . . . . . . . . .±25mA
DC VCC or Ground Current, ICC or IGND . . . . . . . . . . . . . . . . . .±50mA
Operating Conditions
Temperature Range (TA) . . . . . . . . . . . . . . . . . . . . . -55oC to 125oC
Supply Voltage Range, VCC
HC Types . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .2V to 6V
HCT Types . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .4.5V to 5.5V
DC Input or Output Voltage, VI, VO . . . . . . . . . . . . . . . . . 0V to VCC
Input Rise and Fall Time
2V . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1000ns (Max)
4.5V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 500ns (Max)
6V . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 400ns (Max)
Package Thermal Impedance, θJA (see Note 1):
E (PDIP) Package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 67oC/W
M (SOIC) Package. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 73oC/W
NS (SOP) Package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 64oC/W
PW (TSSOP) Package . . . . . . . . . . . . . . . . . . . . . . . . . 108oC/W
Maximum Junction Temperature . . . . . . . . . . . . . . . . . . . . . . . 150oC
Maximum Storage Temperature Range . . . . . . . . . .-65oC to 150oC
Maximum Lead Temperature (Soldering 10s) . . . . . . . . . . . . . 300oC
(SOIC - Lead Tips Only)
CAUTION: Stresses above those listed in “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress only rating and operation
of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied.
NOTE:
1. The package thermal impedance is calculated in accordance with JESD 51-7.
DC Electrical Specifications
PARAMETER
HC TYPES
High Level Input
Voltage
Low Level Input
Voltage
High Level Output
Voltage
CMOS Loads
High Level Output
Voltage
TTL Loads
Low Level Output
Voltage
CMOS Loads
Low Level Output
Voltage
TTL Loads
Input Leakage
Current
Quiescent Device
Current
SYMBOL
TEST
CONDITIONS
VI (V) IO (mA)
VCC
(V)
VIH
-
-
2
4.5
6
VIL
-
-
2
4.5
6
VOH VIH or VIL -0.02
2
-0.02
4.5
-0.02
6
-
-
-4
4.5
-5.2
6
VOL VIH or VIL 0.02
2
0.02
4.5
0.02
6
-
-
4
4.5
5.2
6
II
VCC or
-
6
GND
ICC
VCC or
0
6
GND
25oC
-40oC TO 85oC -55oC TO 125oC
MIN TYP MAX MIN MAX MIN MAX UNITS
1.5
-
-
1.5
-
1.5
-
V
3.15
-
-
3.15
-
3.15
-
V
4.2
-
-
4.2
-
4.2
-
V
-
-
0.5
-
0.5
-
0.5
V
-
-
1.35
-
1.35
-
1.35
V
-
-
1.8
-
1.8
-
1.8
V
1.9
-
-
1.9
-
1.9
-
V
4.4
-
-
4.4
-
4.4
-
V
5.9
-
-
5.9
-
5.9
-
V
-
-
-
-
-
-
-
V
3.98
-
-
3.84
-
3.7
-
V
5.48
-
-
5.34
-
5.2
-
V
-
-
0.1
-
0.1
-
0.1
V
-
-
0.1
-
0.1
-
0.1
V
-
-
0.1
-
0.1
-
0.1
V
-
-
-
-
-
-
-
V
-
-
0.26
-
0.33
-
0.4
V
-
-
0.26
-
0.33
-
0.4
V
-
-
±0.1
-
±1
-
±1
µA
-
-
8
-
80
-
160
µA
3




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