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32-bit MCU. R7FA6M2AD3CFP Datasheet

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32-bit MCU. R7FA6M2AD3CFP Datasheet
















R7FA6M2AD3CFP MCU. Datasheet pdf. Equivalent













Part

R7FA6M2AD3CFP

Description

32-bit MCU



Feature


Cover Datasheet Renesas RA6M2 Group 32 32-Bit MCU Renesas Advanced (RA) Famil y Renesas RA6 Series Datasheet All in formation contained in these materials, including products and product specifi cations, represents information on the product at the time of publication and is subject to change by Renesas Electro nics Corp. without notice. Please revie w the latest infor.
Manufacture

Renesas

Datasheet
Download R7FA6M2AD3CFP Datasheet


Renesas R7FA6M2AD3CFP

R7FA6M2AD3CFP; mation published by Renesas Electronics Corp. through various means, including the Renesas Electronics Corp. website ( http://www.renesas.com). www.renesas.c om Rev.1.10 May 2021 RA6M2 Group Data sheet Leading performance 120-MHz Arm® Cortex®-M4 core, up to 1-MB code flas h memory, 384-KB SRAM, Capacitive Touch Sensing Unit, Ethernet MAC Controller, USB 2.0 Full-Speed,.


Renesas R7FA6M2AD3CFP

SDHI, Quad SPI, security and safety fea tures, and advanced analog. Features ■ Arm Cortex-M4 Core with Floating Po int Unit (FPU) Armv7E-M architecture w ith DSP instruction set Maximum operat ing frequency: 120 MHz Support for 4-G B address space On-chip debugging syst em: JTAG, SWD, and ETM Boundary scan a nd Arm Memory Protection Unit (Arm MPU) ■ Memory Up to 1-M.


Renesas R7FA6M2AD3CFP

B code flash memory (40 MHz zero wait st ates) 32-KB data flash memory (125,000 erase/write cycles) Up to 384-KB SRAM Flash Cache (FCACHE) Memory Protecti on Units (MPU) Memory Mirror Function (MMF) 128-bit unique ID ■ Connectivi ty Ethernet MAC Controller (ETHERC) E thernet DMA Controller (EDMAC) USB 2.0 Full-Speed (USBFS) module - On-chip tr ansceiver Serial Co.




Part

R7FA6M2AD3CFP

Description

32-bit MCU



Feature


Cover Datasheet Renesas RA6M2 Group 32 32-Bit MCU Renesas Advanced (RA) Famil y Renesas RA6 Series Datasheet All in formation contained in these materials, including products and product specifi cations, represents information on the product at the time of publication and is subject to change by Renesas Electro nics Corp. without notice. Please revie w the latest infor.
Manufacture

Renesas

Datasheet
Download R7FA6M2AD3CFP Datasheet




 R7FA6M2AD3CFP
Cover
Renesas RA6M2 Group
32
32-Bit MCU
Renesas Advanced (RA) Family
Renesas RA6 Series
Datasheet
All information contained in these materials, including products and product specifications,
represents information on the product at the time of publication and is subject to change by
Renesas Electronics Corp. without notice. Please review the latest information published by
Renesas Electronics Corp. through various means, including the Renesas Electronics Corp.
website (http://www.renesas.com).
www.renesas.com
Rev.1.10 May 2021




 R7FA6M2AD3CFP
RA6M2 Group
Datasheet
Leading performance 120-MHz Arm® Cortex®-M4 core, up to 1-MB code flash memory, 384-KB SRAM, Capacitive
Touch Sensing Unit, Ethernet MAC Controller, USB 2.0 Full-Speed, SDHI, Quad SPI, security and safety features, and
advanced analog.
Features
Arm Cortex-M4 Core with Floating Point Unit (FPU)
Armv7E-M architecture with DSP instruction set
Maximum operating frequency: 120 MHz
Support for 4-GB address space
On-chip debugging system: JTAG, SWD, and ETM
Boundary scan and Arm Memory Protection Unit (Arm MPU)
Memory
Up to 1-MB code flash memory (40 MHz zero wait states)
32-KB data flash memory (125,000 erase/write cycles)
Up to 384-KB SRAM
Flash Cache (FCACHE)
Memory Protection Units (MPU)
Memory Mirror Function (MMF)
128-bit unique ID
Connectivity
Ethernet MAC Controller (ETHERC)
Ethernet DMA Controller (EDMAC)
USB 2.0 Full-Speed (USBFS) module
- On-chip transceiver
Serial Communications Interface (SCI) with FIFO × 10
Serial Peripheral Interface (SPI) × 2
I2C bus interface (IIC) × 3
Controller Area Network (CAN) × 2
Serial Sound Interface Enhanced (SSIE)
SD/MMC Host Interface (SDHI) × 2
Quad Serial Peripheral Interface (QSPI)
IrDA interface
Sampling Rate Converter (SRC)
External address space
- 8-bit or 16-bit bus space is selectable per area
- SDRAM support
Analog
12-bit A/D Converter (ADC12) with 3 sample-and-hold circuits
each × 2
12-bit D/A Converter (DAC12) × 2
High-Speed Analog Comparator (ACMPHS) × 6
Temperature Sensor (TSN)
Timers
General PWM Timer 32-bit Enhanced High Resolution
(GPT32EH) × 4
General PWM Timer 32-bit Enhanced (GPT32E) × 4
General PWM Timer 32-bit (GPT32) × 6
Asynchronous General-Purpose Timer (AGT) × 2
Watchdog Timer (WDT)
Safety
Error Correction Code (ECC) in SRAM
SRAM parity error check
Flash area protection
ADC self-diagnosis function
Clock Frequency Accuracy Measurement Circuit (CAC)
Cyclic Redundancy Check (CRC) calculator
Data Operation Circuit (DOC)
Port Output Enable for GPT (POEG)
Independent Watchdog Timer (IWDT)
GPIO readback level detection
Register write protection
Main oscillator stop detection
Illegal memory access
System and Power Management
Low power modes
Realtime Clock (RTC) with calendar and VBATT support
Event Link Controller (ELC)
DMA Controller (DMAC) × 8
Data Transfer Controller (DTC)
Key Interrupt Function (KINT)
Power-on reset
Low Voltage Detection (LVD) with voltage settings
Security and Encryption
AES128/192/256
3DES/ARC4
SHA1/SHA224/SHA256/MD5
GHASH
RSA/DSA/ECC
True Random Number Generator (TRNG)
Human Machine Interface (HMI)
Capacitive Touch Sensing Unit (CTSU)
Parallel Data Capture Unit (PDC)
Multiple Clock Sources
Main clock oscillator (MOSC) (8 to 24 MHz)
Sub-clock oscillator (SOSC) (32.768 kHz)
High-speed on-chip oscillator (HOCO) (16/18/20 MHz)
Middle-speed on-chip oscillator (MOCO) (8 MHz)
Low-speed on-chip oscillator (LOCO) (32.768 kHz)
IWDT-dedicated on-chip oscillator (15 kHz)
Clock trim function for HOCO/MOCO/LOCO
Clock out support
General-Purpose I/O Ports
Up to 110 input/output pins
- Up to 1 CMOS input
- Up to 109 CMOS input/output
- Up to 21 input/output 5 V tolerant
- Up to 18 high current (20 mA)
Operating Voltage
VCC: 2.7 to 3.6 V
Operating Temperature and Packages
Ta = -40°C to +105°C
- 145-pin LGA (7 mm × 7 mm, 0.5 mm pitch)
- 144-pin LQFP (20 mm × 20 mm, 0.5 mm pitch)
- 100-pin LQFP (14 mm × 14 mm, 0.5 mm pitch)
R01DS0357EJ0110 Rev.1.10
May 14, 2021
Page 2 of 100




 R7FA6M2AD3CFP
RA6M2 Group
1. Overview
1. Overview
The MCU integrates multiple series of software- and pin-compatible Arm®-based 32-bit cores that share a common set
of Renesas peripherals to facilitate design scalability and efficient platform-based product development.
The MCU in this series incorporates a high-performance Arm Cortex®-M4 core running up to 120 MHz with the
following features:
Up to 1-MB code flash memory
384-KB SRAM
Capacitive Touch Sensing Unit (CTSU)
Ethernet MAC Controller (ETHERC), USBFS, SD/MMC Host Interface
Quad Serial Peripheral Interface (QSPI)
Security and safety features
12-bit A/D Converter (ADC12)
12-bit D/A Converter (DAC12)
Analog peripherals.
Note: For more details of the MCU specifications, refer to RA6M2 Group User's Manual: Hardware.
1.1 Function Outline
Table 1.1
Arm core
Feature
Arm Cortex-M4 core
Functional description
Maximum operating frequency: up to 120 MHz
Arm Cortex-M4 core:
- Revision: r0p1-01rel0
- ARMv7E-M architecture profile
- Single precision floating-point unit compliant with the ANSI/IEEE Std 754-2008.
Arm Memory Protection Unit (Arm MPU):
- Armv7 Protected Memory System Architecture
- 8 protect regions.
SysTick timer:
- Driven by SYSTICCLK (LOCO) or ICLK.
Table 1.2
Memory
Feature
Code flash memory
Data flash memory
Memory Mirror Function (MMF)
Option-setting memory
SRAM
Standby SRAM
Functional description
Maximum 1-MB code flash memory. See section 53, Flash Memory.
32-KB data flash memory. See section 53, Flash Memory.
The Memory Mirror Function (MMF) can be configured to mirror the target application image
load address in code flash memory to the application image link address in the 23-bit unused
memory space (memory mirror space addresses). Your application code is developed and
linked to run from this MMF destination address. The application code does not need to know
the load location where it is stored in code flash memory. See section 5, Memory Mirror
Function (MMF) in User’s Manual.
The option-setting memory determines the state of the MCU after a reset. See section 7,
Option-Setting Memory in User’s Manual.
On-chip high-speed SRAM with either parity-bit or Error Correction Code (ECC). The first 32
KB of SRAM0 error correction capability using ECC. Parity check is performed for other areas.
See section 51, SRAM in User’s Manual.
On-chip SRAM that can retain data in Deep Software Standby mode. See section 52, Standby
SRAM in User’s Manual.
R01DS0357EJ0110 Rev.1.10
May 14, 2021
Page 3 of 100




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