83210

Low Skew, 1-to-10, HSTL Fanout Buffer 83210 Data Sheet GENERAL DESCRIPTION The 83210 is a low skew, 1-to-10 HSTL Fanout Buffer. The class II HSTL outputs are balanced push-pull in design, capable of delivering 16mA into a 10pF load. This class allows both source series termination and symmetrically double parallel termination. FEATURES Ten single-ended HSTL outputs One single-ended HSTL clock input Maximum input frequency: 150MHz Output skew: 110ps (maximum) Part-to-part skew: 2ns (maximum) 1.5V power supply 0°C to 85°C ambient operating temperature Available in lead-free (RoHS 6) package BLOCK DIAGRAM IN nOE Pulldown PIN ASSIGNMENT GND Q2 Q1 VDD VDD Q0 GND GND Q0 32 31 30 29 28 27 26 25 Q1 VDD 1 24 GND GND 2 23 Q3 VDD 3 22 Q4 nOE 4 21 VDD Q8 GND 5 ICS83210 20 VDD Q9 IN 6 19 Q5 VDD 7 18 Q6 GND 8 17 GND 9 10 11 12 13 14 15 16 GND Q7 Q8 VDD VDD Q9 GND GND 32-Lead TQFP 7mm x 7mm x 1.0mm package body Y package Top View ©2016 Integrated Device Technology, Inc 1 Revision A March 10, 2016 83210 Data Sheet TABLE 1. PIN DESCRIPTIONS Number 1, 3, 7, 12, 13, 20, 21, 28, 29 2, 5, 8, 9, 10, 16, 17, 24, 25, 31, 32 4 Name V DD GND nOE Type Power Description Power supply pins. Power Power supply ground. Input Output enable/disable input pin. When LOW, outputs Qx outputs are Pulldown enabled. When HIGH, Qx outputs are disabled low. LVCMOS/LVTTL interface levels. 5 IN Input Single-ended reference clock input. HSTL interface levels...