Document
ICS97UL PA8 77A
1.8V Low-Power Wide-Range Frequency Clock Driver
Recommended Application: • DDR2 Memory Modules / Zero Delay Board Fan Out • Provides complete DDR DIMM logic solution with
ICSSSTU32864/SSTUF32864/SSTUF32866/ SSTUA32864/SSTUA32866/SSTUA32S868/ SSTUA32S865/SSTUA32S869
Product Description/Features: • Low skew, low jitter PLL clock driver • 1 to 10 differential clock distribution (SSTL_18) • Feedback pins for input to output synchronization • Spread Spectrum tolerant inputs • Auto PD when input signal is at a certain logic state
Switching Characteristics: • Period jitter: 40ps (DDR2-400/533)
30ps (DDR2-667/800) • Half-period jitter: 60ps (DDR2-400/533)
50ps (DDR2-667/800) • OUTPUT - OUTPUT skew: 40ps (DDR2-400/533)
30ps (DDR2-667/800) • CYCLE - CYCLE jitter 40ps
Block Diagram
Pin Configuration
123456 A B C D E F G H J K
52-Ball BGA
Top View
1
A CLKT1 B CLKC1 C CLKC2 D CLKT2 E CLK_INT F CLK_INC G AGND H AVDD J CLKT3 K CLKC3
2
CLKT0 GND GND VDDQ VDDQ VDDQ VDDQ GND GND CLKC4
3
CLKC0 GND NB VDDQ NB NB VDDQ NB GND CLKT4
4
CLKC5 GND NB VDDQ NB NB VDDQ NB GND CLKT9
5
CLKT5 G ND G ND OS VDDQ OE VDDQ G ND G ND CLKC9
6
CLKT6 CLKC6 CLKC7 CLKT7 FB_INT FB_INC FB_OUTC FB_OUTT CLKT8 CLKC8
OE OS AVDD
Powerdown Control and Test Logic
LD* or OE LD*, OS or OE
LD*
PLL bypass
CLK_INT CLK_INC
10K-100k PLL
GND
FB_INT FB_INC
* The Logic Detect (LD) powers down the device when a logic low is applied to both CLK_INT and CLK_INC.
CLKT0 CLKC0
CLKT1 CLKC1
CLKT2 CLKC2
CLKT3 CLKC3 CLKT4 CLKC4
CLKT5 CLKC5
CLKT6 CLKC6
CLKT7 CLKC7
CLKT8 CLKC8
CLKT9 CLKC9
VDDQ 1 CLKC2 CLKT2 CLK_INT CLK_INC VDDQ AGND AVDD VDDQ
GND 10
FB_OUTT FB_OUTC
CLKT3 CLKC3 CLKC4 CLKT4 VDDQ CLKT9 CLKC9 CLKC8 CLKT8 VDDQ
CLKC1 CLKT1 CLKT0 CLKC0 VDDQ CLKC5 CLKT5 CLKT6 CLKC6 VDDQ
40
31
ICS97ULPA877A
11
20
40-Pin MLF
30 CLKC7 CLKT7 VDDQ FB_INT FB_INC FB_OUTC FB_OUTT VDDQ OE
21 OS
1088B—01/18/06
ICS97UL PA8 77A
Pin Descriptions
Terminal Name AGND AV
DD
CLK_INT CLK_INC FB_INT FB_INC FB_OUTT FB_OUTC
OE OS GND VDDQ CLKT[0:9] CLKC[0:9] NB
Description
Analog Ground Analog power Clock input with a (10K-100K Ohm) pulldown resistor Complentary clock input with a (10K-100K Ohm) pulldown resistor Feedback clock input Complementary feedback clock input Feedback clock output Complementary feedback clock output Output Enable (Asynchronous) Output Select (tied to GND or VDDQ) Ground Logic and output power Clock outputs Complementary clock outputs No ball
Electrical Characteristics Ground 1.8 V nominal Differential input Differential input Differential input Differential input Differential output Differential output LVCMOS input LVCMOS input Ground 1.8V nominal Differential outputs Differential outputs
The PLL clock buffer, ICS97ULPA877A, is designed for a VDDQ of 1.8 V, a AVDD of 1.8 V and differential data input and output levels. Package options include a plastic 52-ball VFBGA and a 40-pin MLF.
ICS97ULPA877A is a zero delay buffer that distributes a differential clock input pair (CLK_INT, CLK_INC) to ten differential pair of clock outputs (CLKT[0:9], CLKC[0:9]) and one differential pair feedback clock outputs (FB_OUTT, FBOUTC). The clock outputs are controlled by the input clocks (CLK_INT, CLK_INC), the feedback clocks (FB_INT, FB_INC), the LVCMOS program pins (OE, OS) and the Analog Power input (AVDD).When OE is low, the outputs (except FB_OUTT/FB_OUTC) are disabled while the internal PLL continues to maintain its locked-in frequency. OS (Output Select) is a program pin that must be tied to GND or VDDQ.When OS is high, OE will function as described above.When OS is low, OE has no effect on CLKT7/CLKC7 (they are free running in addition to FB_OUTT/FB_OUTC).When AVDD is grounded, the PLL is turned off and bypassed for test purposes.
When both clock signals (CLK_INT, CLK_INC) are logic low, the device will enter a low power mode. An input logic detection circuit on the differential inputs, independent from the input buffers, will detect the logic low level and perform a low power state where all outputs, the feedback and the PLL are OFF.When the inputs transition from both being logic low to being differential signals, the PLL will be turned back on, the inputs and outputs will be enabled and the PLL will obtain phase lock between the feedback clock pair (FB_INT, FB_INC) and the input clock pair (CLK_INT, CLK_INC) within the specified stabilization time tSTAB.
The PLL in ICS97ULPA877A clock driver uses the input clocks (CLK_INT, CLK_INC) and the feedback clocks (FB_INT, FB_INC) to provide high-performance, low-skew, low-jitter output differential clocks (CLKT[0:9], CLKC[0:9]). ICS97ULPA877A is also able to track Spread Spectrum Clocking (SSC) for reduced EMI.
ICS97ULPA877A is characterized for operation from 0°C to 70°C.
1088B—01/18/06
2
ICS97UL PA8 77A
Function Table
Inputs
Outputs
AVDD OE OS CLK_INT CLK_INT CLKT
CLKC FB_OUTT FB_OUTC
GND
HX
L
H
L
H
L
H
GND
HX
H
L
H
L
H
L
GND
LH
L
H
*L(.