SN74LVC3G04

SN74LVC3G04 www.ti.com SCES363L – AUGUST 2001 – REVISED NOVEMBER 2013 Triple Inverter Gate Check for Samples: SN74LVC3G04 FEATURES 1 2 Available in the Texas Instruments NanoFree™ Package Supports 5-V VCC Operation Inputs Accept Voltages to 5.5 V Max tpd of 4.1 ns at 3.3 V Low Power Consumption, 10-µA Max ICC ±24-mA Output Drive at 3.3 V Typical VOLP (Output Ground Bounce) <0.8 V at VCC = 3.3 V, TA = 25°C Typical VOHV (Output VOH Undershoot) >2 V at VCC = 3.3 V, TA = 25°C Ioff Supports Live Insertion, Partial-PowerDown Mode, and Back-Drive Protection Can Be Used as a Down Translator to Translate Inputs From a Max of 5.5 V Down to the VCC Level Latch-Up Performance Exceeds 100 mA Per JESD 78, Class II ESD Protection Exceeds JESD 22 – 2000-V Human-Body Model (A114-A) – 200-V Machine Model (A115-A) – 1000-V Charged-Device Model (C101) DESCRIPTION This triple inverter is designed for 1.65-V to 5.5-V VCC operation. The SN74LVC3G04 device performs the Boolean function Y = A. NanoFree™ package technology is a major breakthrough in IC packaging concepts, using the die as the package. This device is fully specified for partial-power-down applications using Ioff. The Ioff circuitry disables the outputs, preventing damaging current backflow through the device when it is powered down. DCT PACKAGE (TOP VIEW) 1A 1 3Y 2 2A 3 GND 4 8 VCC 7 1Y 6 3A 5 2Y DCU PACKAGE (TOP VIEW) 1A 1 3Y 2 2A 3 GND 4 8 VCC 7 1Y 6 3A 5 2Y YZP PACKAGE (BOTTOM VIE...