32-BIT EDGE-TRIGGERED D-TYPE FLIP-FLOP
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FEATURES
• Member of the Texas Instruments Widebus™ Family
• Operates From 1.65 V to 3.6 V • Inputs Accept Vo...
Description
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FEATURES
Member of the Texas Instruments Widebus™ Family
Operates From 1.65 V to 3.6 V Inputs Accept Voltages to 5.5 V Max tpd of 4.5 ns at 3.3 V Typical VOLP (Output Ground Bounce) < 0.8 V
at VCC = 3.3 V, TA = 25°C Typical VOHV (Output VOH Undershoot) > 2 V
at VCC = 3.3 V, TA = 25°C
SN74LVC32374A 32-BIT EDGE-TRIGGERED D-TYPE FLIP-FLOP
WITH 3-STATE OUTPUTS
SCES407A – JULY 2002 – REVISED MARCH 2005
Ioff Supports Partial-Power-Down Mode Operation
Supports Mixed-Mode Signal Operation on All Ports (5-V Input and Output Voltages With 3.3-V VCC)
Latch-Up Performance Exceeds 100 mA Per JESD 78, Class II
ESD Protection Exceeds JESD 22 – 2000-V Human-Body Model (A114-A)
– 1000-V Charged-Device Model (C101)
DESCRIPTION/ORDERING INFORMATION
This 32-bit edge-triggered D-type flip-flop is designed for 1.65-V to 3.6-V VCC operation.
The SN74LVC32374A is particularly suitable for implementing buffer registers, I/O ports, bidirectional bus drivers, and working registers. It can be used as four 8-bit flip-flops, two 16-bit flip-flops, or one 32-bit flip-flop. On the positive transition of the clock (CLK) input, the Q outputs of the flip-flop take on the logic levels set up at the data (D) inputs.
A buffered output-enable (OE) input can be used to place the eight outputs in either a normal logic state (high or low logic levels) or the high-impedance state. In the high-impedance state, the outputs neither load nor drive the bus lines significantly. The high-impe...
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