SN54BCT8373A

SN54BCT8373A, SN74BCT8373A SCAN TEST DEVICES WITH OCTAL D-TYPE LATCHES SCBS044F – JUNE 1990 – REVISED JULY 1996 D Members of the Texas Instruments SCOPE ™ Family of Testability Products D Octal Test-Integrated Circuits D Functionally Equivalent to ’F373 and ’BCT373 in the Normal-Function Mode D Compatible With the IEEE Standard 1149.1-1990 (JTAG) Test Access Port and Boundary-Scan Architecture D Test Operation Synchronous to Test Access Port (TAP) D Implement Optional Test Reset Signal by Recognizing a Double-High-Level Voltage (10 V ) on TMS Pin D SCOPE ™ Instruction Set – IEEE Standard 1149.1-1990 Required Instructions, Optional INTEST, CLAMP, and HIGHZ – Parallel Signature Analysis at Inputs – Pseudo-Random Pattern Generation From Outputs – Sample Inputs / Toggle Outputs D Package Options Include Plastic Small-Outline (DW) Packages, Ceramic Chip Carriers (FK), and Standard Plastic and Ceramic 300-mil DIPs (JT, NT) description The ’BCT8373A scan test devices with octal D-type latches are members of the Texas Instruments SCOPE™ testability integratedcircuit family. This family of devices supports IEEE Standard 1149.1-1990 boundary scan to facilitate testing of complex circuit board assemblies. Scan access to the test circuitry is accomplished via the 4-wire test access port (TAP) interface. SN54BCT8373A . . . JT PACKAGE SN74BCT8373A . . . DW OR NT PACKAGE (TOP VIEW) LE 1 1Q 2 2Q 3 3Q 4 4Q 5 GND 6 5Q 7 6Q 8 7Q 9 8Q 10 TDO 11 TMS 12 24 OE 23 1D 22 2D 21 3D 20 4D 19 5D 18 V...