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SN74BCT573 Dataheets PDF



Part Number SN74BCT573
Manufacturers Texas Instruments
Logo Texas Instruments
Description OCTAL TRANSPARENT D-TYPE LATCHES
Datasheet SN74BCT573 DatasheetSN74BCT573 Datasheet (PDF)

D Operating Voltage Range of 4.5 V to 5.5 V D State-of-the-Art BiCMOS Design Significantly Reduces ICCZ D Full Parallel Access for Loading SN54BCT573 . . . J OR W PACKAGE SN74BCT573 . . . DW, N, OR NS PACKAGE (TOP VIEW) SN54BCT573, SN74BCT573 OCTAL TRANSPARENT D-TYPE LATCHES WITH 3-STATE OUTPUTS SCBS071B − AUGUST 1990 − REVISED MARCH 2003 D ESD Protection Exceeds JESD 22 − 2000-V Human-Body Model (A114-A) − 200-V Machine Model (A115-A) − 1000-V Charged-Device Model (C101) SN54BCT573 . . . FK PA.

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D Operating Voltage Range of 4.5 V to 5.5 V D State-of-the-Art BiCMOS Design Significantly Reduces ICCZ D Full Parallel Access for Loading SN54BCT573 . . . J OR W PACKAGE SN74BCT573 . . . DW, N, OR NS PACKAGE (TOP VIEW) SN54BCT573, SN74BCT573 OCTAL TRANSPARENT D-TYPE LATCHES WITH 3-STATE OUTPUTS SCBS071B − AUGUST 1990 − REVISED MARCH 2003 D ESD Protection Exceeds JESD 22 − 2000-V Human-Body Model (A114-A) − 200-V Machine Model (A115-A) − 1000-V Charged-Device Model (C101) SN54BCT573 . . . FK PACKAGE (TOP VIEW) 1Q VCC OE 1D 2D OE 1 1D 2 2D 3 3D 4 4D 5 5D 6 6D 7 7D 8 8D 9 GND 10 20 VCC 19 1Q 18 2Q 17 3Q 16 4Q 15 5Q 14 6Q 13 7Q 12 8Q 11 LE description/ordering information 8D GND LE 3 2 1 20 19 3D 4 18 2Q 4D 5 17 3Q 5D 6 16 4Q 6D 7 15 5Q 7D 8 14 6Q 9 10 11 12 13 8Q 7Q These 8-bit latches feature 3-state outputs designed specifically for driving highly capacitive or relatively low-impedance loads. They are particularly suitable for implementing buffer registers, I/O ports, bidirectional bus drivers, and working registers. The eight latches of the ’BCT573 devices are transparent D-type latches. While the latch-enable (LE) input is high, the Q outputs follow the data (D) inputs. When the latch enable is taken low, the Q outputs are latched at the logic levels that were set up at the D inputs. A buffered output-enable (OE) input can be used to place the eight outputs in either a normal logic state (high or low logic levels) or the high-impedance state. In the high-impedance state, the outputs neither load nor drive the bus lines significantly. The high-impedance state and increased drive provide the capability to drive bus lines without interface or pullup components. To ensure the high-impedance state during power up or power down, OE should be tied to VCC through a pullup resistor; the minimum value of the resistor is determined by the current-sinking capability of the driver. OE does not affect internal operations of the latches. Old data can be retained or new data can be entered while the outputs are in the high-impedance state. ORDERING INFORMATION TA PACKAGE† ORDERABLE PART NUMBER TOP-SIDE MARKING PDIP − N Tube SN74BCT573N SN74BCT573N 0°C to 70°C SOIC − DW Tube Tape and reel SN74BCT573DW SN74BCT573DWR BCT573 SOP − NS Tape and reel SN74BCT573NSR BCT573 CDIP − J Tube SNJ54BCT573J SNJ54BCT573J −55°C to 125°C CFP − W Tube SNJ54BCT573W SNJ54BCT573W LCCC − FK Tube SNJ54BCT573FK SNJ54BCT573FK † Package drawings, standard packing quantities, thermal data, symbolization, and PCB design guidelines are available at www.ti.com/sc/package. Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet. PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of Texas Instruments standard wa.


SN54BCT573 SN74BCT573 SN74BCT573N


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