SN74BCT29854

BiCMOS Process With TTL Inputs and Outputs State-of-the-Art BiCMOS Design Significantly Reduces Standby Current Flow-Through Pinout (All Inputs on Opposite Side From Outputs) Functionally Equivalent to AMD Am29854 High-Speed Bus Transceiver With Parity Generator/ Checker Parity-Error Flag With Open-Collector Output Latch for Storage of the Parity-Error Flag Package Options Include Plastic Small-Outline (DW) Packages and Standard Plastic 300-mil DIPs (NT) SN74BCT29854 8ĆBIT TO 9ĆBIT PARITY BUS TRANSCEIVER ą SCBS257 − SEPTEMBER 1987 − REVISED NOVEMBER 1993 DW OR NT PACKAGE (TOP VIEW) OEA 1 A1 2 A2 3 A3 4 A4 5 A5 6 A6 7 A7 8 A8 9 ERR 10 CLR 11 GND 12 24 VCC 23 B1 22 B2 21 B3 20 B4 19 B5 18 B6 17 B7 16 B8 15 PARITY 14 OEB 13 LE description The SN74BCT29854 is an 8-bit to 9-bit parity transceiver designed for asynchronous communication between data buses. When data is transmitted from the A to B bus, a parity bit is generated. When data is transmitted from the B to A bus with its corresponding parity bit, the parity-error (ERR) output will indicate whether or not an error in the B data has occurred. The output-enable (OEA, OEB) inputs can be used to disable the device so that the buses are effectively isolated. A 9-bit parity generator/ checker generates a parity-odd (PARITY) output and monitors the parity of the I/O ports with an open-collector parity-error (ERR) flag. ERR can be either passed, sampled, stored, or cleared from the latch using the latch-enable ...