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PHASE-LOCKED LOOP. TLC2932 Datasheet

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PHASE-LOCKED LOOP. TLC2932 Datasheet






TLC2932 LOOP. Datasheet pdf. Equivalent




TLC2932 LOOP. Datasheet pdf. Equivalent





Part

TLC2932

Description

HIGH-PERFORMANCE PHASE-LOCKED LOOP



Feature


TLC2932 HIGH-PERFORMANCE PHASE-LOCKED LO OP D Voltage-Controlled Oscillator (VC O) Section: – Complete Oscillator Usi ng Only One External Bias Resistor (RBI AS) – Lock Frequency: 22 MHz to 50 MH z (VDD = 5 V ±5%, TA = – 20°C to 75 °C, ×1 Output) 11 MHz to 25 MHz (VDD = 5 V ±5%, TA = – 20°C to 75°C, × 1/2 Output) – Output Frequency . . . ×1 and ×1/2 Selectable D Phase-Frequ.
Manufacture

Texas Instruments

Datasheet
Download TLC2932 Datasheet


Texas Instruments TLC2932

TLC2932; ency Detector (PFD) Section Includes a H igh-Speed Edge-Triggered Detector With Internal Charge Pump D Independent VCO, PFD Power-Down Mode D Thin Small-Outli ne Package (14 terminal) D CMOS Technol ogy D Typical Applications: – Frequen cy Synthesis – Modulation/Demodulatio n – Fractional Frequency Division D A pplication Report Available† D CMOS I nput Logic Level SLAS097E.


Texas Instruments TLC2932

– SEPTEMBER 1994 – REVISED MAY 1997 PW PACKAGE† (TOP VIEW) LOGIC VDD 1 SELECT 2 VCO OUT 3 FIN – A 4 FIN – B 5 PFD OUT 6 LOGIC GND 7 14 VCO VDD 13 BIAS 12 VCO IN 11 VCO GND 10 VCO INHIBIT 9 PFD INHIB IT 8 NC † Available in tape and re el only and ordered as the TLC2932IPWLE . NC – No internal connection descri ption The TLC2932 is designed f.


Texas Instruments TLC2932

or phase-locked-loop (PLL) systems and i s composed of a voltage-controlled osci llator (VCO) and an edge-triggered-type phase frequency detector (PFD). The os cillation frequency range of the VCO is set by an external bias resistor (RBIA S). The VCO has a 1/2 frequency divider at the output stage. The high-speed PF D with internal charge pump detects the phase difference .

Part

TLC2932

Description

HIGH-PERFORMANCE PHASE-LOCKED LOOP



Feature


TLC2932 HIGH-PERFORMANCE PHASE-LOCKED LO OP D Voltage-Controlled Oscillator (VC O) Section: – Complete Oscillator Usi ng Only One External Bias Resistor (RBI AS) – Lock Frequency: 22 MHz to 50 MH z (VDD = 5 V ±5%, TA = – 20°C to 75 °C, ×1 Output) 11 MHz to 25 MHz (VDD = 5 V ±5%, TA = – 20°C to 75°C, × 1/2 Output) – Output Frequency . . . ×1 and ×1/2 Selectable D Phase-Frequ.
Manufacture

Texas Instruments

Datasheet
Download TLC2932 Datasheet




 TLC2932
TLC2932
HIGH-PERFORMANCE PHASE-LOCKED LOOP
D Voltage-Controlled Oscillator (VCO)
Section:
– Complete Oscillator Using Only One
External Bias Resistor (RBIAS)
– Lock Frequency:
22 MHz to 50 MHz (VDD = 5 V ±5%,
TA = – 20°C to 75°C, ×1 Output)
11 MHz to 25 MHz (VDD = 5 V ±5%,
TA = – 20°C to 75°C, ×1/2 Output)
– Output Frequency . . . ×1 and ×1/2
Selectable
D Phase-Frequency Detector (PFD) Section
Includes a High-Speed Edge-Triggered
Detector With Internal Charge Pump
D Independent VCO, PFD Power-Down Mode
D Thin Small-Outline Package (14 terminal)
D CMOS Technology
D Typical Applications:
– Frequency Synthesis
– Modulation/Demodulation
– Fractional Frequency Division
D Application Report Available
D CMOS Input Logic Level
SLAS097E – SEPTEMBER 1994 – REVISED MAY 1997
PW PACKAGE†
(TOP VIEW)
LOGIC VDD
1
SELECT
2
VCO OUT
3
FIN – A
4
FIN – B
5
PFD OUT
6
LOGIC GND
7
14
VCO VDD
13
BIAS
12
VCO IN
11
VCO GND
10
VCO INHIBIT
9
PFD INHIBIT
8
NC
Available in tape and reel only and ordered as the
TLC2932IPWLE.
NC – No internal connection
description
The TLC2932 is designed for phase-locked-loop (PLL) systems and is composed of a voltage-controlled
oscillator (VCO) and an edge-triggered-type phase frequency detector (PFD). The oscillation frequency range
of the VCO is set by an external bias resistor (RBIAS). The VCO has a 1/2 frequency divider at the output stage.
The high-speed PFD with internal charge pump detects the phase difference between the reference frequency
input and signal frequency input from the external counter. Both the VCO and the PFD have inhibit functions,
which can be used as a power-down mode. The TLC2932 is suitable for use as a high-performance PLL due
to the high speed and stable oscillation capability of the device.
functional block diagram
FIN –A
FIN –B
PFD INHIBIT
4 Phase
5 Frequency 6
9 Detector
VCO IN
BIAS
PFD OUT VCO INHIBIT
SELECT
12
13
10
Voltage-
Controlled
3
2 Oscillator
VCO OUT
AVAILABLE OPTIONS
PACKAGE
TA
SMALL OUTLINE
(PW)
– 20°C to 75°C TLC2932IPWLE
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
TLC2932 Phase-Locked-Loop Building Block With Analog Voltage-Controlled Oscillator and Phase Frequency Detector (SLAA011).
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of Texas Instruments
standard warranty. Production processing does not necessarily include
testing of all parameters.
Copyright © 1997, Texas Instruments Incorporated
POST OFFICE BOX 655303 DALLAS, TEXAS 75265
1




 TLC2932
TLC2932
HIGH-PERFORMANCE PHASE-LOCKED LOOP
SLAS097E – SEPTEMBER 1994 – REVISED MAY 1997
Terminal Functions
TERMINAL
NAME
NO.
FIN – A
4
FIN – B
5
LOGIC GND
7
LOGIC VDD
1
NC
8
PFD INHIBIT
9
PFD OUT
6
BIAS
13
SELECT
2
VCO IN
12
VCO INHIBIT
10
VCO GND
11
VCO OUT
3
VCO VDD
14
I/O
DESCRIPTION
I Input reference frequency f(REF IN) is applied to FIN – A.
I Input for VCO external counter output frequency f(FIN – B). FIN – B is nominally provided from the external
counter.
GND for the internal logic.
Power supply for the internal logic. This power supply should be separate from VCO VDD to reduce
cross-coupling between supplies.
No internal connection.
I PFD inhibit control. When PFD INHIBIT is high, PFD output is in the high-impedance state, see Table 3.
O PFD output. When the PFD INHIBIT is high, PFD output is in the high-impedance state.
I Bias supply. An external resistor (RBIAS) between VCO VDD and BIAS supplies bias for adjusting the
oscillation frequency range.
I VCO output frequency select. When SELECT is high, the VCO output frequency is × 1/2 and when low, the
output frequency is × 1, see Table 1.
I VCO control voltage input. Nominally the external loop filter output connects to VCO IN to control VCO
oscillation frequency.
I VCO inhibit control. When VCO INHIBIT is high, VCO OUT is low (see Table 2).
GND for VCO.
O VCO output. When the VCO INHIBIT is high, VCO output is low.
Power supply for VCO. This power supply should be separated from LOGIC VDD to reduce cross-coupling
between supplies.
detailed description
VCO oscillation frequency
The VCO oscillation frequency is determined by an external resistor (RBIAS) connected between the VCO VDD
and the BIAS terminals. The oscillation frequency and range depends on this resistor value. The bias resistor
value for the minimum temperature coefficient is nominally 3.3 kwith 3-V at the VCO VDD terminal and
nominally 2.2 kwith 5-V at the VCO VDD terminal. For the lock frequency range refer to the recommended
operating conditions. Figure 1 shows the typical frequency variation and VCO control voltage.
VCO Oscillation Frequency Range
Bias Resistor (RBIAS)
1/2 VDD
VCO Control Voltage (VCO IN)
Figure 1. VCO Oscillation Frequency
2
POST OFFICE BOX 655303 DALLAS, TEXAS 75265




 TLC2932
TLC2932
HIGH-PERFORMANCE PHASE-LOCKED LOOP
SLAS097E – SEPTEMBER 1994 – REVISED MAY 1997
VCO output frequency 1/2 divider
The TLC2932 SELECT terminal sets the fosc or 1/2 fosc VCO output frequency as shown in Table 1. The 1/2
fosc output should be used for minimum VCO output jitter.
Table 1. VCO Output 1/2 Divider Function
SELECT
Low
High
VCO OUTPUT
fosc
1/2 fosc
VCO inhibit function
The VCO has an externally controlled inhibit function which inhibits the VCO output. A high level on the VCO
INHIBIT terminal stops the VCO oscillation and powers down the VCO. The output maintains a low level during
the power-down mode, refer to Table 2.
Table 2. VCO Inhibit Function
VCO INHIBIT
Low
High
VCO OSCILLATOR
Active
Stopped
VCO OUTPUT
Active
Low level
IDD(VCO)
Normal
Power Down
PFD operation
The PFD is a high-speed, edge-triggered detector with an internal charge pump. The PFD detects the phase
difference between two frequency inputs supplied to FIN–A and FIN–B as shown in Figure 2. Nominally the
reference is supplied to FIN–A, and the frequency from the external counter output is fed to FIN–B.
FIN– A
FIN– B
PFD OUT
VOH
Hi-Z
VOL
Figure 2. PFD Function Timing Chart
PFD output control
A high level on the PFD INHIBIT terminal places the PFD output in the high-impedance state and the PFD stops
phase detection as shown in Table 3. A high level on the PFD INHIBIT terminal also can be used as the
power-down mode for the PFD.
Table 3. VCO Output Control Function
PFD INHIBIT
Low
High
DETECTION
Active
Stopped
PFD OUTPUT
Active
Hi-Z
IDD(PFD)
Normal
Power Down
POST OFFICE BOX 655303 DALLAS, TEXAS 75265
3



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