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BUILDING BLOCK. TLC2942 Datasheet

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BUILDING BLOCK. TLC2942 Datasheet






TLC2942 BLOCK. Datasheet pdf. Equivalent




TLC2942 BLOCK. Datasheet pdf. Equivalent





Part

TLC2942

Description

HIGH-PERFORMANCE DUAL PHASE-LOCKED LOOP BUILDING BLOCK



Feature


TLC2942 HIGH-PERFORMANCE DUAL PHASE-LOCK ED LOOP BUILDING BLOCK SLAS146B – NO VEMBER 1996 – REVISED JUNE 1997 D Du al TLC2932 by Multichip Module (MCM) D B PACKAGE Technology (TOP VIEW) D Vo ltage-Controlled Oscillator (VCO) Secti on: – Complete Oscillator Using Only One External Bias Resistor (RBIAS) – Recommended Lock Frequency Range: 22 MH z to 50 MHz (VDD = 5 V ±5%.
Manufacture

Texas Instruments

Datasheet
Download TLC2942 Datasheet


Texas Instruments TLC2942

TLC2942; , TA = – 20°C to 75°C, ×1 Output) 1 1 MHz to 25 MHz (VDD = 5 V ±5%, TA = 20°C to 75°C, ×1/2 Output) – Ou tput Frequency . . . ×1 and ×1/2 Sele ctable LOGIC VDD1 1 SELECT1 2 VCO OUT1 3 FIN–A1 4 FIN–B1 5 PFD OUT1 6 LOG IC GND1 7 GND 8 NC 9 NC 10 38 VCO VDD1 37 BIAS1 36 VCOIN1 35 VCO GND1 34 VCOI NHIBIT1 33 PFD INHIBIT1 32 NC 31 GND 30 NC 29 NC D Includes a High-Speed Ed.


Texas Instruments TLC2942

ge-Triggered Phase Frequency Detector (P FD) With Internal Charge Pump D Indepen dent VCO, PFD Power-Down Mode NC 11 GN D 12 LOGIC VDD2 13 SELECT2 14 VCO OUT2 15 28 NC 27 GND 26 VCO VDD2 25 BIAS2 2 4 VCOIN2 description FIN–A2 16 FIN B2 17 23 VCO GND2 22 VCOINHIBIT2 Th e TLC2942 is a multichip module product that PFD OUT2 18 21 PFD INHIBIT2 us es two TLC2932 chips. .


Texas Instruments TLC2942

The TLC2932 chip is LOGIC GND2 19 20 NC composed of a voltage-controlled osci llator and an edge-triggered phase fre quency detector. The NC – No internal connection oscillation frequency rang e of each VCO is set by an external bi as resistor (RBIAS) and each VCO output can be a ×1 or ×1/2 output frequency . Each high speed PFD with internal cha rge pump detects the p.

Part

TLC2942

Description

HIGH-PERFORMANCE DUAL PHASE-LOCKED LOOP BUILDING BLOCK



Feature


TLC2942 HIGH-PERFORMANCE DUAL PHASE-LOCK ED LOOP BUILDING BLOCK SLAS146B – NO VEMBER 1996 – REVISED JUNE 1997 D Du al TLC2932 by Multichip Module (MCM) D B PACKAGE Technology (TOP VIEW) D Vo ltage-Controlled Oscillator (VCO) Secti on: – Complete Oscillator Using Only One External Bias Resistor (RBIAS) – Recommended Lock Frequency Range: 22 MH z to 50 MHz (VDD = 5 V ±5%.
Manufacture

Texas Instruments

Datasheet
Download TLC2942 Datasheet




 TLC2942
TLC2942
HIGH-PERFORMANCE DUAL PHASE-LOCKED LOOP BUILDING BLOCK
SLAS146B – NOVEMBER 1996 – REVISED JUNE 1997
D Dual TLC2932 by Multichip Module (MCM)
DB PACKAGE
Technology
(TOP VIEW)
D Voltage-Controlled Oscillator (VCO)
Section:
– Complete Oscillator Using Only One
External Bias Resistor (RBIAS)
– Recommended Lock Frequency Range:
22 MHz to 50 MHz (VDD = 5 V ±5%,
TA = – 20°C to 75°C, ×1 Output)
11 MHz to 25 MHz (VDD = 5 V ±5%,
TA = – 20°C to 75°C, ×1/2 Output)
– Output Frequency . . . ×1 and ×1/2
Selectable
LOGIC VDD1 1
SELECT1 2
VCO OUT1 3
FIN–A1 4
FIN–B1 5
PFD OUT1 6
LOGIC GND1 7
GND 8
NC 9
NC 10
38 VCO VDD1
37 BIAS1
36 VCOIN1
35 VCO GND1
34 VCOINHIBIT1
33 PFD INHIBIT1
32 NC
31 GND
30 NC
29 NC
D Includes a High-Speed Edge-Triggered
Phase Frequency Detector (PFD) With
Internal Charge Pump
D Independent VCO, PFD Power-Down Mode
NC 11
GND 12
LOGIC VDD2 13
SELECT2 14
VCO OUT2 15
28 NC
27 GND
26 VCO VDD2
25 BIAS2
24 VCOIN2
description
FIN–A2 16
FIN–B2 17
23 VCO GND2
22 VCOINHIBIT2
The TLC2942 is a multichip module product that
PFD OUT2 18
21 PFD INHIBIT2
uses two TLC2932 chips. The TLC2932 chip is LOGIC GND2 19
20 NC
composed of a voltage-controlled oscillator and
an edge-triggered phase frequency detector. The NC – No internal connection
oscillation frequency range of each VCO is set by
an external bias resistor (RBIAS) and each VCO output can be a ×1 or ×1/2 output frequency. Each high speed
PFD with internal charge pump detects the phase difference between the reference frequency input and signal
frequency input from the external counter. The VCO and the PFD have inhibit functions that can be used as a
power-down mode. The high-speed and stable oscillation capability of the TLC2932 makes the TLC2942
suitable for use in dual high-performance phase-locked loop (PLL) systems.
AVAILABLE OPTIONS
PACKAGE
TA
SMALL OUTLINE
(DB)
–20°C to 75°C
TLC2942IDB
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of Texas Instruments
standard warranty. Production processing does not necessarily include
testing of all parameters.
POST OFFICE BOX 655303 DALLAS, TEXAS 75265
Copyright © 1997, Texas Instruments Incorporated
1




 TLC2942
TLC2942
HIGH-PERFORMANCE DUAL PHASE-LOCKED LOOP BUILDING BLOCK
SLAS146B – NOVEMBER 1996 – REVISED JUNE 1997
functional block diagram
VCO
VCO
INHIBIT1 VCO OUT1 VCO OUT2 INHIBIT2
SELECT1
SELECT2
34
2
3 15 14 22
36
VCOIN1
VCO_1
VCO_2
24
VCOIN2
4
FIN–A1
5
FIN–B1
PFD_1
PFD_2
16
FIN–A2
17 FIN–B2
33
6 18
21
PFD OUT1 PFD OUT2
PFD INHIBIT1
PFD INHIBIT2
2
POST OFFICE BOX 655303 DALLAS, TEXAS 75265




 TLC2942
TLC2942
HIGH-PERFORMANCE DUAL PHASE-LOCKED LOOP BUILDING BLOCK
SLAS146B – NOVEMBER 1996 – REVISED JUNE 1997
Terminal Functions
TERMINAL
I/
NAME
NO. O
DESCRIPTION
BIAS1
37
I VCO1 bias supply. An external resistor (RBIAS1) between VCO VDD1 and BIAS1 supplies bias for adjusting
the oscillation frequency range.
BIAS2
25
I VCO2 bias supply. An external resistor (RBIAS2) between VCO VDD2 and BIAS2 supplies bias for adjusting
the oscillation frequency range.
FIN–A1
FIN–A2
4
I Input reference frequency 1. The frequency f(REF IN)1 is applied to FIN-A1.
16
I Input reference frequency 2. The frequency f(REF IN)2 is applied to FIN-A2.
FIN–B1
5
I Input for VCO1 external counter output frequency f(FIN-B)1. FIN-B1 is nominally provided from the external
counter (see Figure 28).
FIN–B2
17
I Input for VCO2 external counter output frequency f(FIN-B)2. FIN-B2 is nominally provided from the external
counter (see Figure 28).
GND
8, 12,
27,31
Ground
LOGIC VDD1
1
Logic1 supply voltage. LOGIC VDD1 supplies voltage to internal logic 1. LOGIC VDD1 should be separate
from the other supply lines to reduce cross-coupling between power supplies.
LOGIC VDD2
13
Logic2 supply voltage. LOGIC VDD2 supplies voltage to internal logic 2. LOGIC VDD2 should be separate
from the other supply lines to reduce cross-coupling between power supplies.
LOGIC GND1
7
Ground for the internal logic 1
LOGIC GND2
19
Ground for the internal logic 2
NC
9, 10, 11,
No internal connection
20, 28,
29, 30,
32
PFD INHIBIT1
33
I PFD inhibit 1 control. When PFD INHIBIT1 is high, PFD OUT1 is in the high-impedance state (see
Table 4).
PFD INHIBIT2
21
I PFD inhibit 2 control. When PFD INHIBIT2 is high, PFD OUT2 is in the high-impedance state (see
Table 5).
PFD OUT1
6
O PFD1 output. When the PFD INHIBIT1 is high, PFD OUT1 is in the high-impedance state.
PFD OUT2
SELECT1
SELECT2
18
O PFD2 output. When the PFD INHIBIT2 is high, PFD OUT2 is in the high-impedance state.
2
I
 VCO1 output frequency select. When SELECT1 is high, the VCO1 output frequency is 1/2 and when
 SELECT1 is low, the output frequency is 1 (see Table 1).
14
I
 VCO2 output frequency select. When SELECT2 is high, the VCO2 output frequency is 1/2 and when
 SELECT2 is low, the output frequency is 1 (see Table 1).
VCO GND1
35
Ground for VCO1
VCO GND2
23
Ground for VCO2
VCOINHIBIT1
34
I VCO1 inhibit control. When VCOINHIBIT1 is high, VCO OUT1 is low (see Table 2).
VCOINHIBIT2
22
O VCO2 inhibit control. When VCOINHIBIT2 is high, VCO OUT2 is low (see Table 3).
VCO OUT1
3
O VCO1 output. When VCOINHIBIT1 is high, VCO OUT1 is low.
VCO OUT2
15
VCO2 output. When VCOINHIBIT2 is high, VCO OUT2 is low.
VCO VDD1
VCO VDD2
VCOIN1
38
VCO1 supply voltage. VCO VDD1 supplies voltage for VCO1. VCO VDD1 should be separated from LOGIC
VDD1 and LOGIC VDD2 and VCO VDD2 to reduce cross-coupling between power supplies.
26
VCO2 supply voltage. VCO VDD2 supplies voltage for VCO2. VCO VDD2 should be separated from LOGIC
VDD1 and LOGIC VDD2 and VCO VDD1 to reduce cross-coupling between power supplies.
36
I VCO1 control voltage input. Nominally the external loop filter output1 connects to VCOIN1 to control VCO1
oscillation frequency.
VCOIN2
24
I VCO2 control voltage input. Nominally the external loop filter output2 connects to VCOIN2 to control VCO2
oscillation frequency.
POST OFFICE BOX 655303 DALLAS, TEXAS 75265
3



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