High-Speed Differential Line Receivers
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SN55LVDS32, SN65LVDS32, SN65LV...
Description
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SN55LVDS32, SN65LVDS32, SN65LVDS3486, SN65LVDS9637
SLLS262R – JULY 1997 – REVISED DECEMBER 2014
SNx5LVDS3xxxx High-Speed Differential Line Receivers
1 Features
1 Meet or Exceed the Requirements of ANSI TIA/EIA-644 Standard
Operate With a Single 3.3-V Supply Designed for Signaling Rates of up to 150 Mbps
(See ) Differential Input Thresholds ±100 mV Max Typical Propagation Delay Time of 2.1 ns Power Dissipation 60 mW Typical Per Receiver at
Maximum Data Rate Bus-Terminal ESD Protection Exceeds 8 kV Low-Voltage TTL (LVTTL) Logic Output Levels Pin Compatible With AM26LS32, MC3486, and
μA9637 Open-Circuit Fail-Safe Cold Sparing for Space and High-Reliability
Applications Requiring Redundancy
2 Applications
Wireless Infrastructure Telecom Infrastructure Printer
3 Description
The SN55LVDS32, SN65LVDS32, SN65LVDS3486, and SN65LVDS9637 devices are differential line receivers that implement the electrical characteristics of low-voltage differential signaling (LVDS). This signaling technique lowers the output voltage levels of 5-V differential standard levels (such as EIA/TIA422B) to reduce the power, increase the switching speeds, and allow operation with a 3.3-V supply rail. Any of the differential receivers provides a valid logical output state with a ±100-mV differential input voltage within the input common-mode voltage range. The input common-mode voltage range al...
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