2SJ574

2SJ574 Silicon P Channel MOS FET High Speed Switching Features Low on-resistance RDS = 1.1 Ω typ. (VGS = –10 V, ID = –150 mA) RDS = 2.2 Ω typ. (VGS = –4 V, ID = –150 mA) 4 V gate drive device. Small package (MPAK) Outline RENESAS Package code: PLSP0003ZB-A (Package name: MPAK) Note: Marking is BP 3 G 1 2 Preliminary Datasheet R07DS0574EJ0500 Rev.5.00 Jan 10, 2014 D 1. Source 2. Gate 3. Drain S Absolute Maximum Ratings Item Symbol Drain to source voltage Gate to source voltage Drain current Drain peak current Body-drain diode reverse drain current Channel dissipation VDSS VGSS ID ID(pulse)Note1 IDR Pch Note 2 Channel temperature Tch Storage temperature Tstg Notes: 1. PW ≤ 10 µs, duty cycle ≤ 1% 2. Value on the alumina ceramic board (12.5 x 20 x 0.7mm) Ratings –30 ±20 –300 –1.2 –300 400 150 –55 to +150 (Ta = 25°C) Unit V V mA A mA mW °C °C R07DS0574EJ0500 Rev.5.00 Jan 10, 2014 Page 1 of 7 2SJ574 Preliminary Electrical Characteristics (Ta = 25°C) Item Symbol Min Typ Max Unit Test Conditions Drain to source breakdown voltage V(BR)DSS –30 — — V ID = –100 μA, VGS = 0 Gate to source breakdown voltage V(BR)GSS ±20 — — V IG = ±100 μA, VDS = 0 Zero gate voltage drain current IDSS — — –1 μA VDS = –30 V, VGS = 0 Gate to source leak current IGSS — — ±5 μA VGS = ±16 V, VDS = 0 Gate to source cutoff voltage Static drain to source on state resistance Forward transfer admittance VGS(off) –1.3 — –2.3 V ID = –10 μA, VDS = –5 V RDS(on) ...