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74F573 Data Sheet

Octal Transparent D-Type Latches

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74F573
SN54F573, SN74F573 OCTAL TRANSPARENT DĆTYPE LATCHES WITH 3ĆSTATE OUTPUTS SDFS011A − MARCH 1987 − REVISED OCTOBER 1993 • Eight Latches in a Single Package • 3-State Bus-Driving True Outputs • Full Parallel Access for Loading • Buffered Control Inputs • Package Options Include Plastic Small-Outline Packages, Ceramic Chip Carriers, and Standard Plastic and Ceramic 300-mil DIPs description These 8-bit latches feature 3-state outputs designed specifically for driving highly capacitive or relatively low-impedance loads. They are particularly suitable for implementing buffer registers, I/O ports, bidirectional bus drivers, and working registers. SN54F573 . . . J PACKAGE SN74F573 . . . DW OR N PACKAGE (TOP VIEW) OE 1 1D 2 2D 3 3D 4 4D 5 5D 6 6D 7 7D 8 8D 9 GND 10 20 VCC 19 1Q 18 2Q 17 3Q 16 4Q 15 5Q 14 6Q 13 7Q 12 8Q 11 LE SN54F573 . . . FK PACKAGE (TOP VIEW) 1Q VCC OE 1D 2D The eight latches of the ′F573 are transparent D-type latches. While the latch enable (LE) input is high, the.
74F573

Download 74F573 Datasheet
SN54F573, SN74F573 OCTAL TRANSPARENT DĆTYPE LATCHES WITH 3ĆSTATE OUTPUTS SDFS011A − MARCH 1987 − REVISED OCTOBER 1993 • Eight Latches in a Single Package • 3-State Bus-Driving True Outputs • Full Parallel Access for Loading • Buffered Control Inputs • Package Options Include Plastic Small-Outline Packages, Ceramic Chip Carriers, and Standard Plastic and Ceramic 300-mil DIPs description These 8-bit latches feature 3-state outputs designed specifically for driving highly capacitive or relatively low-impedance loads. They are particularly suitable for implementing buffer registers, I/O ports, bidirectional bus drivers, and working registers. SN54F573 . . . J PACKAGE SN74F573 . . . DW OR N PACKAGE (TOP VIEW) OE 1 1D 2 2D 3 3D 4 4D 5 5D 6 6D 7 7D 8 8D 9 GND 10 20 VCC 19 1Q 18 2Q 17 3Q 16 4Q 15 5Q 14 6Q 13 7Q 12 8Q 11 LE SN54F573 . . . FK PACKAGE (TOP VIEW) 1Q VCC OE 1D 2D The eight latches of the ′F573 are transparent D-type latches. While the latch enable (LE) input is high, the Q outputs follow the data (D) inputs. When the latch enable is taken low, the Q outputs are latched at the logic levels set up at the D inputs. A buffered output enable (OE) input can be used to place the eight outputs in either a normal logic state (high or low logic levels) or a highimpedance state. In the high-impedance state, the outputs neither load nor drive the bus lines significantly. The high-impedance state and increased drive provide the capability to drive bus lines without need for.


54F573 74F573 SN54F74


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