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MT9126 Dataheets PDF



Part Number MT9126
Manufacturers MITEL
Logo MITEL
Description Quad ADPCM Transcoder
Datasheet MT9126 DatasheetMT9126 Datasheet (PDF)

CMOS MT9126 ® Quad ADPCM Transcoder Preliminary Information Features • Full duplex transcoder with four encode channels and four decode channels • 32 kb/s, 24 kb/s and 16 kb/s ADPCM coding complying with ITU-T (previously CCITT) G.726 (without 40 kb/s), and ANSI T1.303-1989 • Low power operation, 25 mW typical • Asynchronous 4.096 MHz master clock operation • SSI and ST-BUS interface options • Transparent PCM bypass • Transparent ADPCM bypass • Linear PCM code • No microprocessor control requir.

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CMOS MT9126 ® Quad ADPCM Transcoder Preliminary Information Features • Full duplex transcoder with four encode channels and four decode channels • 32 kb/s, 24 kb/s and 16 kb/s ADPCM coding complying with ITU-T (previously CCITT) G.726 (without 40 kb/s), and ANSI T1.303-1989 • Low power operation, 25 mW typical • Asynchronous 4.096 MHz master clock operation • SSI and ST-BUS interface options • Transparent PCM bypass • Transparent ADPCM bypass • Linear PCM code • No microprocessor control required • Simple interface to Codec devices • Pin selectable µ−Law or A-Law operation • Pin selectable ITU-T or signed magnitude PCM coding • Single 5 volt power supply Applications • Pair gain • Voice mail systems • Wireless telephony systems ISSUE 2 Ordering Information MT9126AE 28 Pin Plastic DIP MT9126AS 28 Pin SOIC -40 °C to +85 °C May 1995 Description The Quad ADPCM Transcoder is a low power, CMOS device capable of four encode and four decode functions per frame. Four 64 kbit/s PCM octets are compressed into four 32, 24 or 16 kbit/s ADPCM words, and four 32, 24 or 16 kbit/s ADPCM words are expanded into four 64 kbit/s PCM octets. The 32, 24 and 16 kbit/s ADPCM transcoding algorithms utilized conform to ITU-T Recommendation G.726 (excluding 40 kbit/s), and ANSI T1.303 - 1989. Switching, on-the-fly, between 32 kbit/s and 24 kbit/s ADPCM, is possible by controlling the appropriate mode select (MS1 - MS6) control pins. All optional functions of the device are pin selectable allowing a simple interface to industry standard codecs, digital phone devices and Layer 1 transceivers. Linear coded PCM is provided to facilitate external DSP functions . ADPCMi ADPCMo ENB1 ENB2/F0od BCLK F0i MCLK C2o EN1 EN2 Full Duplex ADPCM I/O Quad Transcoder PCM I/O PCMo1 PCMi1 PCMo2 PCMi2 Timing Control Decode VDD VSS PWRDN IC MS1 MS2 MS3 A/µ FORMAT MS4 MS5 MS6 LINEAR SEL Figure 1 - Functional Block Diagram 8-33 MT9126 Preliminary Information EN1 1 MCLK 2 F0i 3 C2o 4 BCLK 5 PCMo1 6 PCMi1 7 VSS 8 LINEAR 9 ENB2/F0od 10 ENB1 11 PCMo2 12 PCMi2 13 SEL 14 28 EN2 27 MS6 26 MS5 25 MS4 24 ADPCMo 23 ADPCMi 22 VDD 21 MS3 20 MS2 19 MS1 18 IC 17 PWRDN 16 FORMAT 15 A/µ Figure 2 - Pin Connections Pin Description Pin # 1 2 Name EN1 MCLK Description Enable Strobe 1 (Output). This 8 bit wide, active high strobe is active during the B1 PCM channel in ST-BUS mode. Becomes a single bit, high true pulse when LINEAR=1. In SSI mode this output is high impedance. Master Clock (input). This is a 4.096 MHz (minimum) input clock utilized by the transcoder function; it must be supplied in both ST-BUS and SSI modes of operation. In ST-BUS mode the C4 ST-BUS clock is applied to this pin. This synchronous clock is also used to control the data I/O flow on the PCM and ADPCM input/output pins according to ST-BUS requirements. In SSI mode this master clock input is derived from an external source and may be asynchronous with respect to the 8 kHz frame. MCLK rates greater than 4.096 MHz are acceptable in this mode since the data I/O rate is governed by BCLK. 3 F0i Frame Pulse (Input). Frame synchronization pulse input for ST-BUS operation. SSI operation is enabled by connecting this pin to VSS. 4 C2o 2.048 MHz Clock (Output). This ST-BUS mode bit clock output is the MCLK (C4) input divided by two, inverted, and synchronized to F0i. This output is high-impedance during SSI operation. 5 BCLK Bit Clock (Input). 128 kHz to 4096 kHz bit clock input for both PCM and ADPCM ports; used in SSI mode only. The falling edge of this clock latches data into ADPCMi, PCMi1 and PCMi2. The rising edge clocks data out on ADPCMo, PCMo1 and PCMo2. This input must be tied to VSS for ST-BUS operation. 6 PCMo1 Serial PCM Stream 1 (Output). 128 kbit/s to 4096 kbit/s serial companded/linear PCM output stream. Data are clocked out by rising edge of BCLK in SSI mode. Clocked out by MCLK divided by two in ST-BUS mode. See Figure 14. 7 PCMi1 Serial PCM Stream 1 (Input). 128 kbit/s to 4096 kbit/s serial companded/linear PCM input stream. Data are clocked in on falling edge of BCLK in SSI mode. Clocked in at the 3/4 bit position of MCLK in ST-BUS mode. See Figure 14. 8 VSS Digital Ground. Nominally 0 volts. 9 LINEAR Linear PCM Select (Input). When tied to VDD the PCM I/O ports (PCM1,PCM2) are 16- bit linear PCM. Linear PCM operates only at a bit rate of 2048 kbit/s. Companded PCM is selected when this pin is tied to VSS. See Figures 5 & 8. 8-34 Preliminary Information MT9126 Pin Description Pin # 10 Name Description ENB2/F0od PCM B-Channel Enable Strobe 2 (Input) / Delayed Frame Pulse (Output). SSI operation: ENB2 (Input). An 8-bit wide enable strobe input defining B2 channel (AD)PCM data. A valid 8-bit strobe must be present at this input for SSI operation. See Figures 4 & 6. ST-BUS operation: F0od (Output). This pin is a delayed frame strobe output. When LINEAR=0, this becomes a delayed frame pulse out.


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