54ACT16823

54ACT16823, 74ACT16823 18-BIT BUS-INTERFACE FLIP-FLOPS WITH 3-STATE OUTPUTS SCAS160A – APRIL 1991 – REVISED APRIL 1996 D Members of the Texas Instruments Widebus  Family D Inputs Are TTL-Voltage Compatible D Provide Extra Data Width Necessary for Wider Address/Data Paths or Buses With Parity D Flow-Through Architecture Optimizes PCB Layout D Distributed VCC and GND Pin Configuration Minimizes High-Speed Switching Noise D EPIC (Enhanced-Performance Implanted CMOS) 1-µm Process D Package Options Include Plastic 300-mil Shrink Small-Outline (DL) Packages Using 25-mil Center-to-Center Pin Spacings and 380-mil Fine-Pitch Ceramic Flat (WD) Packages Using 25-mil Center-to-Center Pin Spacings description These 18-bit flip-flops feature 3-state outputs designed specifically for driving highly-capacitive or relatively low-impedance loads. They are particularly suitable for implementing wider buffer registers, I/O ports, parity bus interfacing, and working registers. The ’ACT16823 can be used as two 9-bit flip-flops or one 18-bit flip-flop. With the clock-enable (CLKEN) input low, the D-type flip-flops enter data on the low-to-high transitions of the clock. Taking CLKEN high disables the clock buffer, thus latching the outputs. Taking the clear (CLR) input low causes the Q outputs to go low independently of the clock. 54ACT16823 . . . WD PACKAGE 74ACT16823 . . . DL PACKAGE (TOP VIEW) 1CLR 1 1OE 2 1Q1 3 GND 4 1Q2 5 1Q3 6 VCC 7 1Q4 8 1Q5 9 1Q6 10 GND 11 1Q7 12 1Q8 13 1Q9 14 2Q1 15 2Q...