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54ACT16373 Dataheets PDF



Part Number 54ACT16373
Manufacturers Texas Instruments
Logo Texas Instruments
Description 16-BIT D-TYPE TRANSPARENT LATCHES
Datasheet 54ACT16373 Datasheet54ACT16373 Datasheet (PDF)

SN54ACT16373, 74ACT16373 16-BIT D-TYPE TRANSPARENT LATCHES WITH 3-STATE OUTPUTS SCAS122C − MARCH 1990 − REVISED SEPTEMBER 1996 D Members of the Texas Instruments Widebust Family D Inputs Are TTL-Voltage Compatible D 3-State Bus Driving True Outputs D Full Parallel Access for Loading D Flow-Through Architecture Optimizes PCB Layout D Distributed VCC and GND Pin Configuration Minimizes High-Speed Switching Noise D EPICt (Enhanced-Performance Implanted CMOS) 1-mm Process D 500-mA Typical Latch-Up .

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SN54ACT16373, 74ACT16373 16-BIT D-TYPE TRANSPARENT LATCHES WITH 3-STATE OUTPUTS SCAS122C − MARCH 1990 − REVISED SEPTEMBER 1996 D Members of the Texas Instruments Widebust Family D Inputs Are TTL-Voltage Compatible D 3-State Bus Driving True Outputs D Full Parallel Access for Loading D Flow-Through Architecture Optimizes PCB Layout D Distributed VCC and GND Pin Configuration Minimizes High-Speed Switching Noise D EPICt (Enhanced-Performance Implanted CMOS) 1-mm Process D 500-mA Typical Latch-Up Immunity at 125°C D Package Options Include Shrink Small-Outline (DL) 300-mil Packages Using 25-mil Center-to-Center Pin Spacings and 380-mil Fine-Pitch Ceramic Flat (WD) Packages Using 25-mil Center-to-Center Pin Spacings description The SN54ACT16373 and 74ACT16373 are 16-bit D-type transparent latches with 3-state outputs designed specifically for driving highly capacitive or relatively low-impedance loads. They are particularly suitable for implementing buffer registers, I/O ports, bidirectional bus drivers, and working registers. These devices can be used as two 8-bit latches or one 16-bit latch. The Q outputs of the latches follow the data (D) inputs if enable C is taken high. When C is taken low, the Q outputs are latched at the levels set up at the D inputs. SN54ACT16373 . . . WD PACKAGE 74ACT16373 . . . DL PACKAGE (TOP VIEW) 1OE 1 1Q1 2 1Q2 3 GND 4 1Q3 5 1Q4 6 VCC 7 1Q5 8 1Q6 9 GND 10 1Q7 11 1Q8 12 2Q1 13 2Q2 14 GND 15 2Q3 16 2Q4 17 VCC 18 2Q5 19 2Q6 20 GND 21 2Q7 22 2Q8 23 2OE 24 48 1C 47 1D1 46 1D2 45 GND 44 1D3 43 1D4 42 VCC 41 1D5 40 1D6 39 GND 38 1D7 37 1D8 36 2D1 35 2D2 34 GND 33 2D3 32 2D4 31 VCC 30 2D5 29 2D6 28 GND 27 2D7 26 2D8 25 2C A buffered output-enable (OE) input can be used to place the outputs in either a normal logic state (high or low logic levels) or the high-impedance state. In the high-impedance state, the outputs neither load nor drive the bus lines significantly. The high-impedance state and the increased drive provide the capability to drive bus lines in a bus-organized system without need for interface or pullup components. OE does not affect the internal operations of the latches. Old data can be retained or new data can be entered while the outputs are in the high-impedance state. The 74ACT16373 is packaged in TI’s shrink small-outline package, which provides twice the I/O pin count and functionality of standard small-outline packages in the same printed-circuit-board area. The SN54ACT16373 is characterized for operation over the full military temperature range of −55°C to 125°C. The 74ACT16373 is characterized for operation from −40°C to 85°C. Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet. EPIC and Widebus are trademarks of Texas Instruments Incorporated. PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters. Copyright © 1996, Texas Instruments Incorporated • POST OFFICE BOX 655303 DALLAS, TEXAS 75265 1 SN54ACT16373, 74ACT16373 16-BIT D-TYPE TRANSPARENT LATCHES WITH 3-STATE OUTPUTS SCAS122C − MARCH 1990 − REVISED SEPTEMBER 1996 FUNCTION TABLE INPUTS OE C D OUTPUT Q L H H H L H L L L L X Q0 H X X Z logic symbol† 1 1OE 48 1C 24 2OE 25 2C 47 1D1 46 1D2 44 1D3 43 1D4 41 1D5 40 1D6 38 1D7 37 1D8 36 2D1 35 2D2 33 2D3 32 2D4 30 2D5 29 2D6 27 2D7 26 2D8 1EN C1 2EN C4 1D 12 3D 14 2 1Q1 3 1Q2 5 1Q3 6 1Q4 8 1Q5 9 1Q6 11 1Q7 12 1Q8 13 2Q1 14 2Q2 16 2Q3 17 2Q4 19 2Q5 20 2Q6 22 2Q7 23 2Q8 † This symbol is in accordance with ANSI/IEEE Std 91-1984 and IEC Publication 617-12. 2 • POST OFFICE BOX 655303 DALLAS, TEXAS 75265 logic diagram (positive logic) 1 1OE 1C 48 C1 47 1D1 1D SN54ACT16373, 74ACT16373 16-BIT D-TYPE TRANSPARENT LATCHES WITH 3-STATE OUTPUTS SCAS122C − MARCH 1990 − REVISED SEPTEMBER 1996 2OE 24 2C 25 2 C1 1Q1 2D1 36 1D 13 2Q1 To Seven Other Channels To Seven Other Channels absolute maximum ratings over operating free-air temperature range (unless otherwise noted)† Supply voltage range, VCC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −0.5 V to 7 V Input voltage range, VI (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −0.5 V to VCC + 0.5 V Output voltage range, VO (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −0.5 V to VCC + 0.5 V Input clamp current, IIK (VI < 0 or VI > VCC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ±20 mA Output clamp current, IOK (VO < 0 or VO > VCC) . . . . . . . . . . . . . . . . . . . . .


74ACT16373 54ACT16373 74ACT16374


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