Document
D Members of the Texas Instruments
Widebust Family
D Inputs Are TTL-Voltage Compatible D Independent Registers for A and B Buses D Multiplexed Real-Time and Stored Data D Flow-Through Architecture Optimizes
PCB Layout
D Distributed VCC and GND Pin Configuration
Minimizes High-Speed Switching Noise
D EPICt (Enhanced-Performance Implanted
CMOS) 1-mm Process
D 500-mA Typical Latch-Up Immunity at
125°C
D Package Options Include Plastic 300-mil
Shrink Small-Outline (DL) Packages Using 25-mil Center-to-Center Pin Spacings and 380-mil Fine-Pitch Ceramic Flat (WD) Packages Using 25-mil Center-to-Center Pin Spacings
description
The ’ACT16646 are 16-bit bus transceivers consisting of D-type flip-flops and control circuitry with 3-state outputs arranged for multiplexed transmission of data directly from the data bus or from the internal storage registers. The devices can be used as two 8-bit transceivers or one 16-bit transceiver. Data on the A or B bus is clocked into the registers on the low-to-high transition of the appropriate clock (CLKAB or CLKBA) input. Figure 1 illustrates the four fundamental busmanagement functions that can be performed with the bus transceivers and registers.
54ACT16646, 74ACT16646 16-BIT BUS TRANSCEIVERS AND REGISTERS
WITH 3-STATE OUTPUTS
SCAS127B – MARCH 1990 – REVISED APRIL 1996
54ACT16646 . . . WD PACKAGE 74ACT16646 . . . DL PACKAGE
(TOP VIEW)
1DIR 1 1CLKAB 2
1SAB 3 GND 4 1A1 5 1A2 6 VCC 7 1A3 8 1A4 9 1A5 10 GND 11 1A6 12 1A7 13 1A8 14 2A1 15 2A2 16 2A3 17 GND 18 2A4 19 2A5 20 2A6 21 VCC 22 2A7 23 2A8 24 GND 25 2SAB 26 2CLKAB 27 2DIR 28
56 1OE 55 1CLKBA 54 1SBA 53 GND 52 1B1 51 1B2 50 VCC 49 1B3 48 1B4 47 1B5 46 GND 45 1B6 44 1B7 43 1B8 42 2B1 41 2B2 40 2B3 39 GND 38 2B4 37 2B5 36 2B6 35 VCC 34 2B7 33 2B8 32 GND 31 2SBA 30 2CLKBA 29 2OE
Output-enable (OE) and direction-control (DIR) inputs are provided to control the transceiver functions. In the transceiver mode, data present at the high-impedance port may be stored in either register or in both. The select controls (SAB and SBA) can multiplex stored and real-time (transparent mode) data. The circuitry used for select control eliminates the typical decoding glitch that occurs in a multiplexer during the transition between stored and real-time data. DIR determines which bus receives data when OE is low. In the isolation mode (OE high), A data may be stored in one register and/or B data may be stored in the other register.
When an output function is disabled, the input function is still enabled and may be used to store and transmit data. Only one of the two buses, A or B, may be driven at a time.
The 74ACT16646 is packaged in TI’s shrink small-outline package, which provides twice the functionality of standard small-outline packages in the same printed-circuit-board area.
The 54ACT16646 is characterized for operation over the full military temperature range of –55°C to 125°C. The 74ACT16646 is characterized for operation from –40°C to 85°C.
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
EPIC and Widebus are trademarks of Texas Instruments Incorporated.
UNLESS OTHERWISE NOTED this document contains PRODUCTION DATA information current as of publication date. Products conform to specifications per the terms of Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters.
• POST OFFICE BOX 655303 DALLAS, TEXAS 75265
Copyright © 1996, Texas Instruments Incorporated 1
54ACT16646, 74ACT16646
16-BIT BUS TRANSCEIVERS AND REGISTERS WITH 3-STATE OUTPUTS
SCAS127B – MARCH 1990 – REVISED APRIL 1996
BUS A BUS B BUS A BUS B
OE DIR CLKAB CLKBA SAB SBA
L
L
X
X
X
L
REAL-TIME TRANSFER BUS B TO BUS A
OE DIR CLKAB CLKBA SAB SBA
L
H
X
X
L
X
REAL-TIME TRANSFER BUS A TO BUS B
BUS A BUS B BUS A BUS B
OE DIR CLKAB CLKBA SAB SBA
X
X
↑
X
X
X
X
X
X
↑
X
X
H
X
↑
↑
X
X
STORAGE FROM A, B, OR A AND B
OE DIR CLKAB CLKBA SAB SBA
L
L
X
H or L X
H
L
H
H or L
X
H
X
TRANSFER STORED DATA TO A AND/OR B
Figure 1. Bus-Management Functions
2
• POST OFFICE BOX 655303 DALLAS, TEXAS 75265
54ACT16646, 74ACT16646
16-BIT BUS TRANSCEIVERS AND REGISTERS WITH 3-STATE OUTPUTS
SCAS127B – MARCH 1990 – REVISED APRIL 1996
FUNCTION TABLE
INPUTS
OE DIR CLKAB CLKBA SAB SBA
X
X
↑
X
X
X
X
X
X
↑
X
X
DATA I/O†
A1–A8
B1–B8
Input
Unspecified
Unspecified
Input
OPERATION OR FUNCTION
Store A, B unspecified{ Store B, A unspecified{
H
X
↑
↑
X
X
Input
Input
Store A and B data
H
X
H or L H or L
X
X
Input
Input
Isolation, hold storage
L
L
X
X
X
L
Output
Input
Real-time B data to A bus
L
L
X
H or L
X
H
Output
Input
Stored B data to A bus
L
H
X
X
L
X
Input
Output
Real-time A data to B Bus
L
H
H or L
X
H
.