74ACT16841

54ACT16841, 74ACT16841 20-BIT BUS-INTERFACE D-TYPE LATCHES WITH 3-STATE OUTPUTS SCAS174A – MAY 1991 – REVISED APRIL 1996 D Members of the Texas Instruments Widebus ™ Family D Inputs Are TTL-Voltage Compatible D 3-State Outputs Drive Bus Lines Directly D Provide Extra Bus Driving/Latches Necessary for Wider Address/Data Paths or Buses With Parity D Flow-Through Architecture Optimizes PCB Layout D Distributed VCC and GND Pin Configuration Minimizes High-Speed Switching Noise D EPIC™ (Enhanced-Performance Implanted CMOS) 1-µm Process D 500-mA Typical Latch-Up Immunity at 125°C D Package Options Include Plastic Thin Shrink Small-Outline (DGG) Packages, 300-mil Shrink Small-Outline (DL) Packages Using 25-mil Center-to-Center Pin Spacings, and 380-mil Fine-Pitch Ceramic Flat (WD) Packages Using 25-mil Center-to-Center Pin Spacings description These 20-bit latches feature 3-state outputs designed specifically for driving highly capacitive or relatively low-impedance loads. They are particularly suitable for implementing buffer registers, I/O ports, bidirectional bus drivers, and working registers. 54ACT16841 . . . WD PACKAGE 74ACT16841 . . . DGG OR DL PACKAGE (TOP VIEW) 1OE 1 1Q1 2 1Q2 3 GND 4 1Q3 5 1Q4 6 VCC 7 1Q5 8 1Q6 9 1Q7 10 GND 11 1Q8 12 1Q9 13 1Q10 14 2Q1 15 2Q2 16 2Q3 17 GND 18 2Q4 19 2Q5 20 2Q6 21 VCC 22 2Q7 23 2Q8 24 GND 25 2Q9 26 2Q10 27 2OE 28 56 1LE 55 1D1 54 1D2 53 GND 52 1D3 51 1D4 50 VCC 49 1D5 48 1D6 47 1D7 46 GND 45 1D8 44 1D9 43 1D10 42 2D1 41 2D2 40 2D3 39 GN...