74ACT11374

74ACT11374 OCTAL EDGE-TRIGGERED D-TYPE FLIP-FLOP WITH 3-STATE OUTPUTS SCAS217A – JULY 1987 – REVISED APRIL 1996 D Eight D-Type Flip-Flops in a Single Package D 3-State Bus Driving True Outputs D Full Parallel Access for Loading D Inputs Are TTL-Voltage Compatible D Flow-Through Architecture Optimizes PCB Layout D Center-Pin VCC and GND Configurations Minimize High-Speed Switching Noise D EPICt (Enhanced-Performance Implanted CMOS) 1-mm Process D 500-mA Typical Latch-Up Immunity at 125°C D Package Options Include Plastic Small-Outline (DW) and Shrink Small-Outline (DB) Packages, and Standard Plastic 300-mil DIPs (NT) DB, DW, OR NT PACKAGE (TOP VIEW) 1Q 1 2Q 2 3Q 3 4Q 4 GND 5 GND 6 GND 7 GND 8 5Q 9 6Q 10 7Q 11 8Q 12 24 OE 23 1D 22 2D 21 3D 20 4D 19 VCC 18 VCC 17 5D 16 6D 15 7D 14 8D 13 CLK description This 8-bit flip-flop features 3-state outputs designed specifically for driving highly-capacitive or relatively low-impedance loads. It is particularly suitable for implementing buffer registers, I/O ports, bidirectional bus drivers, and working registers. The eight flip-flops of the 74ACT11374 are edge-triggered D-type flip-flops. On the positive transition of the clock (CLK) input, the Q outputs are set to the logic levels set up at the data (D) inputs. An output-enable (OE) input can be used to place the eight outputs in either a normal logic state (high or low logic levels) or a high-impedance state. In the high-impedance state, the outputs neither load nor drive the bus ...