74ACT11623

ą Local Bus-Latch Capability Inputs Are TTL-Voltage Compatible Flow-Through Architecture Optimizes PCB Layout Center-Pin VCC and GND Configurations Minimize High-Speed Switching Noise EPICt (Enhanced-Performance Implanted CMOS) 1-mm Process 500-mA Typical Latch-Up Immunity at 125°C Package Options Include Plastic Small- Outline Packages and Standard Plastic 300-mil DIPs description 74ACT11623 OCTAL BUS TRANSCEIVER WITH 3ĆSTATE OUTPUTS SCAS059A − D2957, JULY 1987 − REVISED APRIL 1993 DW OR NT PACKAGE (TOP VIEW) A1 1 A2 2 A3 3 A4 4 GND 5 GND 6 GND 7 GND 8 A5 9 A6 10 A7 11 A8 12 24 GAB 23 B1 22 B2 21 B3 20 B4 19 VCC 18 VCC 17 B5 16 B6 15 B7 14 B8 13 GBA The 74ACT11623 is designed for asynchronous two-way communication between data buses. The control function implementation allows for maximum flexibility in timing. The device allows data transmission from the A bus to the B bus or from the B bus to the A bus depending upon the logic levels at the enable inputs (GBA and GAB). The enable inputs can be used to disable the device so that the buses are effectively isolated. The dual-enable configuration gives these devices the capability to store data by simultaneous enabling of GBA and GAB. Each output reinforces its input in this transceiver configuration. Thus, when both control inputs are enabled and all other data sources to the two sets of bus lines are at high impedance, both sets of bus lines (16 in all) will remain at their last states. The 8-bit codes appea...