54LS192

PRESETTABLE BCD/DECADE UP/DOWN COUNTER PRESETTABLE 4-BIT BINARY UP/DOWN COUNTER The SN54/74LS192 is an UP/DOWN BCD Decade (8421) Counter and the SN54/74LS193 is an UP/DOWN MODULO-16 Binary Counter. Separate Count Up and Count Down Clocks are used and in either counting mode the www.DataSheet4cUir.ccuoimts operate synchronously. The outputs change state synchronous with the LOW-to-HIGH transitions on the clock inputs. Separate Terminal Count Up and Terminal Count Down outputs are provided which are used as the clocks for a subsequent stages without extra logic, thus simplifying multistage counter designs. Individual preset inputs allow the circuits to be used as programmable counters. Both the Parallel Load (PL) and the Master Reset (MR) inputs asynchronously override the clocks. Low Power . . . 95 mW Typical Dissipation High Speed . . . 40 MHz Typical Count Frequency Synchronous Counting Asynchronous Master Reset and Parallel Load Individual Preset Inputs Cascading Circuitry Internally Provided Input Clamp Diodes Limit High Speed Termination Effects CONNECTION DIAGRAM DIP (TOP VIEW) V CC P0 16 15 MR TC D TC U PL 14 13 12 11 P2 P3 10 9 1 2 3 4 5 6 7 8 P1 Q1 Q 0 CP D CP U Q 2 Q 3 GND NOTE: The Flatpak version has the same pinouts (Connection Diagram) as the Dual In-Line Package. PIN NAMES LOADING (Note a) HIGH LOW CPU CPD MR Count Up Clock Pulse Input Count Down Clock Pulse Input Asynchronous Master Reset (Clear) Input 0.5 U.L. 0.5 ...