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66AK2E02 Dataheets PDF



Part Number 66AK2E02
Manufacturers Texas Instruments
Logo Texas Instruments
Description SoC
Datasheet 66AK2E02 Datasheet66AK2E02 Datasheet (PDF)

Product Folder Sample & Buy Technical Documents Tools & Software Support & Community 66AK2E05, 66AK2E02 SPRS865D – NOVEMBER 2012 – REVISED MARCH 2015 66AK2E0x Multicore DSP+ARM KeyStone II System-on-Chip (SoC) 1 66AK2E0x Features and Description 1.1 Features 1 • ARM® Cortex®-A15 MPCore™ CorePac – Up to Four ARM Cortex-A15 Processor Cores at up to 1.4-GHz – 4MB L2 Cache Memory Shared by all CortexA15 Processor Cores – Full Implementation of ARMv7-A Architecture Instruction Set – 32KB L1 Ins.

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Product Folder Sample & Buy Technical Documents Tools & Software Support & Community 66AK2E05, 66AK2E02 SPRS865D – NOVEMBER 2012 – REVISED MARCH 2015 66AK2E0x Multicore DSP+ARM KeyStone II System-on-Chip (SoC) 1 66AK2E0x Features and Description 1.1 Features 1 • ARM® Cortex®-A15 MPCore™ CorePac – Up to Four ARM Cortex-A15 Processor Cores at up to 1.4-GHz – 4MB L2 Cache Memory Shared by all CortexA15 Processor Cores – Full Implementation of ARMv7-A Architecture Instruction Set – 32KB L1 Instruction and Data Caches per Core – AMBA 4.0 AXI Coherency Extension (ACE) Master Port, Connected to MSMC (Multicore Shared Memory Controller) for Low Latency Access to SRAM and DDR3 • One TMS320C66x DSP Core Subsystem (C66x CorePacs), Each With – 1.4 GHz C66x Fixed/Floating-Point DSP Core • 38.4 GMacs/Core for Fixed Point @ 1.2 GHz • 19.2 GFlops/Core for Floating Point @ 1.2 GHz – Memory • 32K Byte L1P Per CorePac • 32K Byte L1D Per CorePac • 512K Byte Local L2 Per CorePac • Multicore Shared Memory Controller (MSMC) – 2 MB SRAM Memory Shared by DSP CorePacs and ARM CorePac – Memory Protection Unit for Both SRAM and DDR3_EMIF • Multicore Navigator – 8k Multi-Purpose Hardware Queues with Queue Manager – One Packet-Based DMA Engine for ZeroOverhead Transfers • Network Coprocessor – Packet Accelerator Enables Support for • Transport Plane IPsec, GTP-U, SCTP, PDCP • L2 User Plane PDCP (RoHC, Air Ciphering) • 1 Gbps Wire Speed Throughput at 1.5 MPackets Per Second – Security Accelerator Engine Enables Support for • IPSec, SRTP, 3GPP and WiMAX Air Interface, and SSL/TLS Security • ECB, CBC, CTR, F8, A5/3, CCM, GCM, HMAC, CMAC, GMAC, AES, DES, 3DES, Kasumi, SNOW 3G, SHA-1, SHA-2 (256-bit Hash), MD5 • Up to 6.4 Gbps IPSec and 3 Gbps Air Ciphering – Ethernet Subsystem • Eight SGMII Ports with Wire Rate Switching • IEEE1588 v2 (with Annex D/E/F) Support • 8 Gbps Total Ingress/Egress Ethernet BW from Core • Audio/Video Bridging (802.1Qav/D6.0) • QOS Capability • DSCP Priority Mapping • Peripherals – Two PCIe Gen2 Controllers with Support for • Two Lanes per Controller • Supports Up to 5 GBaud – One HyperLink • Supports Connections to Other KeyStone Architecture Devices Providing Resource Scalability • Supports Up to 50 GBaud – 10-Gigabit Ethernet (10-GbE) Switch Subsystem • Two SGMII/XFI Ports with Wire Rate Switching and MACSEC Support • IEEE1588 v2 (with Annex D/E/F) Support – One 72-Bit DDR3/DDR3L Interface with Speeds Up to 1600 MTPS in DDR3 Mode – EMIF16 Interface – Two USB 2.0/3.0 Controllers – USIM Interface – Two UART Interfaces – Three I2C Interfaces – 32 GPIO Pins – Three SPI Interfaces – One TSIP • Support 1024 DS0s • Support 2 Lanes at 32.768/16.3848.192 Mbps Per Lane 1 An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications, intellectual property matters and other important disclaimers. PRODUCTION DATA. 66AK2E05, 66AK2E02 SPRS865D – NOVEMBER 2012 – REVISED MARCH 2015 www.ti.com • System Resources – Three On-Chip PLLs – SmartReflex Automatic Voltage Scaling – Semaphore Module – Thirteen 64-Bit Timers 1.2 Applications • Avionics and Defense • Communications • Industrial Automation • Automation and Process Control – Five Enhanced Direct Memory Access (EDMA) Modules • Commercial Case Temperature: – 0ºC to 85ºC • Extended Case Temperature: – -40ºC to 100ºC • Servers • Enterprise Networking • Cloud Infrastructure 1.3 KeyStone II Architecture TI's KeyStone II Multicore Architecture provides a unified platform for integrating RISC and DSP processing cores along with both hardware/firmware based application-specific acceleration and high performance I/Os. The KeyStone II Multicore Architecture is a proven device architecture to achieve the full performance entitlement through the following major components: TeraNet, Multicore Shared Memory Controller, Multicore Navigator, and HyperLink. TeraNet is a multipoint to multipoint non-blocking switch fabric. Its distributed arbiter provides multiple duplex communication channels in parallel between the master and slave ports without interference. The priority based arbitration mechanism ensures the delivery of the critical traffic delivery in the system. The Multicore Shared Memory Controller (MSMC) is the center of the KeyStone II memory architecture. It provides multiple fast and high-bandwidth channels for processor cores to access DDR and minimizes the access latency by directly connecting to the DDR. The MSMC also provides the flexibility to expand processor cores with little impact at the device level. In addition, it provides multi-bank based fast on-chip SRAM shared among processor cores and IOs. It also provides the I/O cache coherency for the device when the Cortex-A15 processor core is integrated. The Multicore Navigator provides .


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