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ADC124S101 Dataheets PDF



Part Number ADC124S101
Manufacturers Texas Instruments
Logo Texas Instruments
Description 12-Bit A/D Converter
Datasheet ADC124S101 DatasheetADC124S101 Datasheet (PDF)

ADC124S101 www.ti.com SNAS283D – MARCH 2005 – REVISED MARCH 2013 ADC124S101 4 Channel, 500 ksps to 1 Msps, 12-Bit A/D Converter Check for Samples: ADC124S101 FEATURES 1 •2 Specified Over a Range of Sample Rates • Four Input Channels • Variable Power Management • Single Power Supply with 2.7V - 5.25V range APPLICATIONS • Portable Systems • Remote Data Acquisition • Instrumentation and Control Systems KEY SPECIFICATIONS • DNL: +0.9/−0.6 LSB (typ) • INL: ± 0.64 LSB (typ) • SNR: 72.4 dB (typ) • .

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ADC124S101 www.ti.com SNAS283D – MARCH 2005 – REVISED MARCH 2013 ADC124S101 4 Channel, 500 ksps to 1 Msps, 12-Bit A/D Converter Check for Samples: ADC124S101 FEATURES 1 •2 Specified Over a Range of Sample Rates • Four Input Channels • Variable Power Management • Single Power Supply with 2.7V - 5.25V range APPLICATIONS • Portable Systems • Remote Data Acquisition • Instrumentation and Control Systems KEY SPECIFICATIONS • DNL: +0.9/−0.6 LSB (typ) • INL: ± 0.64 LSB (typ) • SNR: 72.4 dB (typ) • Power Consumption – 3V Supply: 4.3 mW (typ) – 5V Supply: 13.1 mW (typ) DESCRIPTION The ADC124S101 is a low-power, four-channel CMOS 12-bit analog-to-digital converter with a highspeed serial interface. Unlike the conventional practice of specifying performance at a single sample rate only, the ADC124S101 is fully specified over a sample rate range of 500 ksps to 1 Msps. The converter is based on a successive-approximation register architecture with an internal track-and-hold circuit. It can be configured to accept up to four input signals at inputs IN1 through IN4. The output serial data is straight binary, and is compatible with several standards, such as SPI™, QSPI™, MICROWIRE, and many common DSP serial interfaces. The ADC124S101 operates with a single supply that can range from +2.7V to +5.25V. Normal power consumption using a +3V or +5V supply is 4.3 mW and 13.1 mW, respectively. The power-down feature reduces the power consumption to just 0.14 µW using a +3V supply, or 0.32 µW using a +5V supply. The ADC124S101 is available in a 10-lead VSSOP package. Operation over the industrial temperature range of −40°C to +85°C. These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam during storage or handling to prevent electrostatic damage to the MOS gates. Table 1. PIN-COMPATIBLE ALTERNATIVES BY RESOLUTION AND SPEED(1) Resolution 12-bit 10-bit 8-bit 50 to 200 ksps ADC124S021 ADC104S021 ADC084S021 Specified for Sample Rate Range of: 200 to 500 ksps 500 ksps to 1 Msps ADC124S051 ADC124S101 ADC104S051 ADC104S101 ADC084S051 ADC084S101 (1) All devices are fully pin and function compatible. Connection Diagram CS VA GND IN4 IN3 1 10 2 9 ADC124S101 3 8 4 7 5 6 SCLK DOUT DIN IN1 IN2 Figure 1. 10-Lead VSSOP See DGS Package 1 Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet. All trademarks are the property of their respective owners. 2 PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of the Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters. Copyright © 2005–2013, Texas Instruments Incorporated ADC124S101 SNAS283D – MARCH 2005 – REVISED MARCH 2013 Block Diagram IN1 . . MUX . IN4 T/H GND 12-Bit SUCCESSIVE APPROXIMATION ADC VA GND CONTROL LOGIC SCLK CS DIN DOUT www.ti.com Figure 2. Pin No. ANALOG I/O 4-7 DIGITAL I/O 10 9 8 1 POWER SUPPLY 2 3 PIN DESCRIPTIONS AND EQUIVALENT CIRCUITS Symbol Description IN1 to IN4 SCLK DOUT DIN CS Analog inputs. These signals can range from 0V to VA. Digital clock input. This clock directly controls the conversion and readout processes. Digital data output. The output samples are clocked out of this pin on falling edges of the SCLK pin. Digital data input. The ADC124S101's Control Register is loaded through this pin on rising edges of the SCLK pin. Chip select. On the falling edge of CS, a conversion process begins. Conversions continue as long as CS is held low. VA GND Positive supply pin. This pin should be connected to a quiet +2.7V to +5.25V source and bypassed to GND with a 1 µF capacitor and a 0.1 µF monolithic capacitor located within 1 cm of the power pin. The ground return for the supply and signals. 2 Submit Documentation Feedback Copyright © 2005–2013, Texas Instruments Incorporated Product Folder Links: ADC124S101 ADC124S101 www.ti.com SNAS283D – MARCH 2005 – REVISED MARCH 2013 Absolute Maximum Ratings(1)(2)(3) Supply Voltage VA Voltage on Any Pin to GND Input Current at Any Pin (4) Package Input Current(4) Power Consumption at TA = 25°C ESD Susceptibility (6) Human Body Model Machine Model Junction Temperature Storage Temperature −0.3V to 6.5V −0.3V to VA +0.3V ±10 mA ±20 mA See (5) 2500V 250V +150°C −65°C to +150°C (1) Absolute Maximum Ratings indicate limits beyond which damage to the device may occur. Operating Ratings indicate conditions for which the device is functional, but do not ensure specific performance limits. For ensured specifications and test conditions, see the Electrical Characteristics. The ensured specifications apply only for the test conditions listed. Some performanc.


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