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ADC12DJ3200 Dataheets PDF



Part Number ADC12DJ3200
Manufacturers Texas Instruments
Logo Texas Instruments
Description RF-Sampling ADC
Datasheet ADC12DJ3200 DatasheetADC12DJ3200 Datasheet (PDF)

Product Folder Order Now Technical Documents Tools & Software Support & Community ADC12DJ3200 SLVSD97A – JUNE 2017 – REVISED APRIL 2020 ADC12DJ3200 6.4-GSPS Single-Channel or 3.2-GSPS Dual-Channel, 12-bit, RF-Sampling Analog-to-Digital Converter (ADC) 1 Features •1 ADC core: – 12-bit resolution – Up to 6.4 GSPS in single-channel mode – Up to 3.2 GSPS in dual-channel mode • Performance specifications: – Noise floor (no signal, VFS = 1.0 VPP-DIFF): – Dual-channel mode: –151.8 dBFS/Hz – Singl.

  ADC12DJ3200   ADC12DJ3200


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Product Folder Order Now Technical Documents Tools & Software Support & Community ADC12DJ3200 SLVSD97A – JUNE 2017 – REVISED APRIL 2020 ADC12DJ3200 6.4-GSPS Single-Channel or 3.2-GSPS Dual-Channel, 12-bit, RF-Sampling Analog-to-Digital Converter (ADC) 1 Features •1 ADC core: – 12-bit resolution – Up to 6.4 GSPS in single-channel mode – Up to 3.2 GSPS in dual-channel mode • Performance specifications: – Noise floor (no signal, VFS = 1.0 VPP-DIFF): – Dual-channel mode: –151.8 dBFS/Hz – Single-channel mode: –154.6 dBFS/Hz – HD2, HD3: –65 dBc up to 3 GHz • Buffered analog inputs with VCMI of 0 V: – Analog input bandwidth (–3 dB): 8.0 GHz – Usable input frequency range: >10 GHz – Full-scale input voltage (VFS, default): 0.8 VPP – Analog input common-mode (VICM): 0 V • Noiseless aperture delay (TAD) adjustment: – Precise sampling control: 19-fs step – Simplifies synchronization and interleaving – Temperature and voltage invariant delays • Easy-to-use synchronization features: – Automatic SYSREF timing calibration – Timestamp for sample marking • JESD204B serial data interface: – Supports subclass 0 and 1 – Maximum lane rate: 12.8 Gbps – Up to 16 lanes allows reduced lane rate • Digital down-converters in dual-channel mode: – Real output: DDC bypass or 2x decimation – Complex output: 4x, 8x, or 16x decimation – Four independent 32-Bit NCOs per DDC • Power consumption: 3 W • Power supplies: 1.1 V, 1.9 V ADC12DJ3200 Measured Input Bandwidth 3 Normalized Gain Response (dB) 0 -3 -6 -9 Single Channel Mode -12 Dual Channel Mode -15 0 2 4 6 8 10 12 Input Frequency (GHz) D_BW 1 2 Applications • Communications testers (802.11ad, 5G) • Satellite communications (SATCOM) • Phased array radar, SIGINT, and ELINT • Synthetic aperture radar (SAR) • Time-of-flight and LIDAR distance measurement • Oscilloscopes and wideband digitizers • Microwave backhaul • RF sampling software-defined radio (SDR) • Spectrometry 3 Description The ADC12DJ3200 device is an RF-sampling, gigasample, analog-to-digital converter (ADC) that can directly sample input frequencies from DC to above 10 GHz. In dual-channel mode, the ADC12DJ3200 can sample up to 3200 MSPS and up to 6400 MSPS in single-channel mode. Programmable tradeoffs in channel count (dual-channel mode) and Nyquist bandwidth (single-channel mode) allow development of flexible hardware that meets the needs of both high channel count or wide instantaneous signal bandwidth applications. Full-power input bandwidth (–3 dB) of 8.0 GHz, with usable frequencies exceeding the –3-dB point in both dual- and singlechannel modes, allows direct RF sampling of L-band, S-band, C-band, and X-band for frequency agile systems. The ADC12DJ3200 uses a high-speed JESD204B output interface with up to 16 serialized lanes and subclass-1 compliance for deterministic latency and multi-device synchronization. The serial output lanes support up to 12.8 Gbps and can be configured to trade-off bit rate and number of lanes. Innovative synchronization features, including noiseless aperture delay (TAD) adjustment and SYSREF windowing, simplify system design for phased array radar and MIMO communications. Optional digital down converters (DDCs) in dual-channel mode allow for reduction in interface rate (real and complex decimation modes) and digital mixing of the signal (complex decimation modes only). Device Information(1) PART NUMBER PACKAGE BODY SIZE (NOM) ADC12DJ3200 FCBGA (144) 10.00 mm × 10.00 mm (1) For all available packages, see the package option addendum at the end of the data sheet. An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications, intellectual property matters and other important disclaimers. PRODUCTION DATA. ADC12DJ3200 SLVSD97A – JUNE 2017 – REVISED APRIL 2020 www.ti.com Table of Contents 1 Features .................................................................. 1 2 Applications ........................................................... 1 3 Description ............................................................. 1 4 Revision History..................................................... 2 5 Pin Configuration and Functions ......................... 4 6 Specifications......................................................... 9 6.1 Absolute Maximum Ratings ...................................... 9 6.2 ESD Ratings.............................................................. 9 6.3 Recommended Operating Conditions..................... 10 6.4 Thermal Information ................................................ 10 6.5 Electrical Characteristics - DC Specifications ......... 11 6.6 Electrical Characteristics - Power Consumption ..... 13 6.7 Electrical Characteristics: AC Specifications (Dual- Channel Mode) ........................................................ 14 6.8 Electrical Characteristics: AC Sp.


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