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ADC12DS105 Data Sheet

A/D Converter

Download ADC12DS105 Datasheet

ADC12DS105
ADC12DS105 www.ti.com SNAS382E – SEPTEMBER 2006 – REVISED APRIL 2013 ADC12DS105 Dual 12-Bit, 105 MSPS A/D Converter with Serial LVDS Outputs Check for Samples: ADC12DS105 FEATURES 1 •2 Clock Duty Cycle Stabilizer • Single +3.0 or 3.3V Supply Operation • Serial LVDS Outputs • Serial Control Interface • Overrange Outputs • 60-pin WQFN Package, (9x9x0.8mm, 0.5mm pin-pitch) APPLICATIONS • High IF Sampling Receivers • Wireless Base Station Receivers • Test and Measurement Equipment • Communications Instrumentation • Portable Instrumentation KEY SPECIFICATIONS • Resolution: 12 Bits • Conversion Rate: 105 MSPS • SNR (fIN = 240 MHz): 68.5 dBFS (typ) • SFDR (fIN = 240 MHz): 83 dBFS (typ) • Full Power Bandwidth: 1 GHz (typ) • Power Consumption: 1 W (typ) DESCRIPTION The ADC12DS105 is a high-performance CMOS analog-to-digital converter capable of converting two analog input signals into 12-bit digital words at rates up to 105 Mega Samples Per Second (MSPS). The digital outputs are serialized.
ADC12DS105

Download ADC12DS105 Datasheet
ADC12DS105 www.ti.com SNAS382E – SEPTEMBER 2006 – REVISED APRIL 2013 ADC12DS105 Dual 12-Bit, 105 MSPS A/D Converter with Serial LVDS Outputs Check for Samples: ADC12DS105 FEATURES 1 •2 Clock Duty Cycle Stabilizer • Single +3.0 or 3.3V Supply Operation • Serial LVDS Outputs • Serial Control Interface • Overrange Outputs • 60-pin WQFN Package, (9x9x0.8mm, 0.5mm pin-pitch) APPLICATIONS • High IF Sampling Receivers • Wireless Base Station Receivers • Test and Measurement Equipment • Communications Instrumentation • Portable Instrumentation KEY SPECIFICATIONS • Resolution: 12 Bits • Conversion Rate: 105 MSPS • SNR (fIN = 240 MHz): 68.5 dBFS (typ) • SFDR (fIN = 240 MHz): 83 dBFS (typ) • Full Power Bandwidth: 1 GHz (typ) • Power Consumption: 1 W (typ) DESCRIPTION The ADC12DS105 is a high-performance CMOS analog-to-digital converter capable of converting two analog input signals into 12-bit digital words at rates up to 105 Mega Samples Per Second (MSPS). The digital outputs are serialized and provided on differential LVDS signal pairs. This converter uses a differential, pipelined architecture with digital error correction and an on-chip sample-and-hold circuit to minimize power consumption and the external component count, while providing excellent dynamic performance. The ADC12DS105 may be operated from a single +3.0V or 3.3V power supply. A powerdown feature reduces the power consumption to very low levels while still allowing fast wake-up time to full operation. The differen.


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