AM1705

Product Folder Order Now Technical Documents Tools & Software Support & Community AM1705 SPRS657F – FEBRUARY 2010 – REVISED JANUARY 2017 AM1705 ARM® Microprocessor 1 Device Overview 1.1 Features 1 375- and 456-MHz ARM926EJ-S™ RISC Core – 32-Bit and 16-Bit (Thumb®) Instructions – Single-Cycle MAC – ARM Jazelle® Technology – Embedded ICE-RT™ for Real-Time Debug ARM9™ Memory Architecture – 16KB of Instruction Cache – 16KB of Data Cache – 8KB of RAM (Vector Table) – 64KB of ROM Enhanced Direct Memory Access Controller 3 (EDMA3): – 2 Transfer Controllers – 32 Independent DMA Channels – 8 Quick DMA Channels – Programmable Transfer Burst Size 128KB of RAM Memory 3.3-V LVCMOS I/Os (Except for USB Interface) Two External Memory Interfaces: – EMIFA – NOR (8-Bit-Wide Data) – NAND (8-Bit-Wide Data) – EMIFB – 16-Bit SDRAM With 128-MB Address Space Three Configurable 16550-Type UART Modules: – UART0 With Modem Control Signals – 16-Byte FIFO – 16x or 13x Oversampling Option – Autoflow Control Signals (CTS, RTS) on UART0 Only Two Serial Peripheral Interfaces (SPIs) Each With One Chip Select Programmable Real-Time Unit Subsystem (PRUSS) – Two Independent Programmable Real-Time Unit (PRU) Cores – 32-Bit Load-Store RISC Architecture – 4KB of Instruction RAM per Core – 512 Bytes of Data RAM per Core – PRUSS can be Disabled Through Software to Save Power – Standard Power-Management Mechanism – Clock Gating – Entire Subsystem Under a Single PSC Clock Gating Domain 1 – Ded...