AM3358-EP

Product Folder Order Now Technical Documents Tools & Software Support & Community AM3358-EP SLUSC35B – APRIL 2015 – REVISED APRIL 2019 AM3358-EP Sitara™ Processor 1 Device Overview 1.1 Features 1 Up to 800-MHz Sitara™ ARM® Cortex®-A8 32‑bit RISC processor – NEON™ SIMD coprocessor – 32KB of L1 instruction and 32KB of data cache with single-error detection (parity) – 256KB of L2 cache with error correcting code (ECC) – 176KB of on-chip boot ROM – 64KB of dedicated RAM – Emulation and debug - JTAG – Interrupt controller (up to 128 interrupt requests) On-chip memory (shared L3 RAM) – 64KB of general-purpose on-chip memory controller (OCMC) RAM – Accessible to all masters – Supports retention for fast wakeup External memory interfaces (EMIF) – mDDR(LPDDR), DDR2, DDR3, DDR3L controller: – mDDR: 200-MHz clock (400-MHz data rate) – DDR2: 266-MHz clock (532-MHz data rate) – DDR3: 400-MHz clock (800-MHz data rate) – DDR3L: 400-MHz clock (800-MHz data rate) – 16-bit data bus – 1GB of total addressable space – Supports one x16 or two x8 memory device configurations – General-purpose memory controller (GPMC) – Flexible 8-bit and 16-bit asynchronous memory interface with up to seven chip selects (NAND, NOR, Muxed-NOR, SRAM) – Uses BCH code to support 4-, 8-, or 16-bit ECC – Uses hamming code to support 1-bit ECC – Error locator module (ELM) – Used in conjunction with the GPMC to locate addresses of data errors from syndrome polynomials generated using a BCH algorithm – Support...