Sitara Processors
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SPRS695D – SEPT...
Description
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SPRS695D – SEPTEMBER 2011 – REVISED JANUARY 2016
AM387x Sitara™ARM® Processors
1 High-Performance System-on-Chip (SoC)
1.1 Features
1
High-Performance Sitara™ ARM® Processors ARM Cortex®-A8 Core
– ARMv7 Architecture In-Order, Dual-Issue, Superscalar Processor Core Neon™ Multimedia Architecture Supports Integer and Floating Point Jazelle® RCT Execution Environment
ARM Cortex-A8 Memory Architecture – 32KB of Instruction and Data Caches – 512KB of L2 Cache – 64KB of RAM, 48KB of Boot ROM
128KB of On-Chip Memory Controller (OCMC) RAM
Imaging Subsystem (ISS) – Camera Sensor Connection Parallel Connection for Raw (up to 16-Bit) and BT.656 or BT.1120 (8- and 16-Bit) – Image Sensor Interface (ISIF) for Handling Image and Video Data From the Camera Sensor – Resizer Resizing Image and Video From 1/16x to 8x Generating Two Different Resizing Outputs Concurrently
Media Controller – Controls the HDVPSS and ISS
SGX530 3D Graphics Engine – Delivers up to 25 MPoly/sec – Universal Scalable Shader Engine (USSE™) – Direct3D™ Mobile, OpenGLES 1.1 and 2.0, OpenVG™ 1.0, OpenMax™ API Support – Advanced Geometry DMA-Driven Operation – Programmable HQ Image Anti-Aliasing
Endianness – ARM Instructions and Data – Little Endian
HD Video Processing Subsystem (HDVPSS) – Two 165-MHz, 2-channel HD Video Capture Modules One 16- or 24-Bit Input or Dual 8-Bit SD Input Cha...
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