AD4130-8

Data Sheet AD4130-8 32 μA, Ultra Low Power, 24-Bit Sigma-Delta ADC with Integrated PGA and FIFO FEATURES ► Ultralow current consumption (typical): ► 32 µA: continuous conversion mode (gain = 128) ► 5 µA: duty cycling mode (ratio = 1/16) ► 0.5 µA: standby mode ► 0.1 µA: power-down mode ► Built-in features for system level power savings: ► Current saving duty cycle ratio: 1/4 or 1/16 ► Smart sequencer and per channel configuration minimizes host processor load ► Deep embedded FIFO minimizes host processor load (depth of 256 samples) ► Autonomous FIFO interrupt functionality, threshold detection ► Single supply as low as 1.71 V increasing battery length ► RMS noise: 25 nV rms at 1.17 SPS (gain = 128) – 48 nV/√Hz ► Up to 22 noise free bits (gain = 1) ► Output data rate: 1.17 SPS to 2.4 kSPS ► Operates from 1.71 V to 3.6 V single supply or ±1.8 V split supplies ► Band gap reference with 15 ppm/°C maximum drift ► PGA with rail-to-rail analog input ► Adaptable sensor interfacing functionality: ► Matched programmable excitation currents for RTDs ► On-chip bias voltage generator for thermocouples FUNCTIONAL BLOCK DIAGRAM ► Low-side power switch for bridge transducers ► Sensor open wire detection ► Internal temperature sensor and oscillator ► Self and system calibration ► Flexible filter options ► Simultaneous 50 Hz/60 Hz rejection (on selected filter options) ► General-purpose outputs ► Diagnostic functionality ► Crosspoint multiplexed inputs ► 8 differential/16 pseudo differential ...