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MC9S08MP16 Dataheets PDF



Part Number MC9S08MP16
Manufacturers NXP
Logo NXP
Description 8-Bit HCS08 CPU
Datasheet MC9S08MP16 DatasheetMC9S08MP16 Datasheet (PDF)

Freescale Semiconductor Data Sheet: Technical Data Document Number: MC9S08MP16 Rev. 2, 08/2011 MC9S08MP16 Series Data Sheet 48-LQFP Case 932-03 32-LQFP Case 873A-03 Features • 8-Bit HCS08 Central Processor Unit (CPU) – Up to 51.34 MHz CPU at 2.7V to 5.5V across temperature range of –40°C to 105°C – Up to 40 MHz CPU at 2.7V to 5.5V across temperature range of –40°C to 125°C – HC08 instruction set with added BGND instruction and additional addressing modes for LDHX and STHX – Support for up t.

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Freescale Semiconductor Data Sheet: Technical Data Document Number: MC9S08MP16 Rev. 2, 08/2011 MC9S08MP16 Series Data Sheet 48-LQFP Case 932-03 32-LQFP Case 873A-03 Features • 8-Bit HCS08 Central Processor Unit (CPU) – Up to 51.34 MHz CPU at 2.7V to 5.5V across temperature range of –40°C to 105°C – Up to 40 MHz CPU at 2.7V to 5.5V across temperature range of –40°C to 125°C – HC08 instruction set with added BGND instruction and additional addressing modes for LDHX and STHX – Support for up to 48 interrupt/reset sources • On-Chip Memory – Up to 16 KB flash memory; read/program/erase over full operating voltage and temperature – Up to 1 KB random-access memory (RAM) – Security circuitry to prevent unauthorized access to RAM and flash memory contents • Power-Saving Modes – Two low power stop modes; reduced power wait mode – Peripheral clock gating can disable clocks to unused modules • Clock Source Options – Oscillator (XOSC) — Loop-control Pierce oscillator; Crystal or ceramic resonator range of 31.25–38.4 kHz or 1–16 MHz – Internal Clock Source (ICS) — Containing a frequency-locked-loop (FLL) controlled by internal or external reference; precision trimming of internal reference allows 0.2% resolutions and 2% deviation over temperature and voltage; supports CPU frequencies up to 51.34 MHz • System Protection – Watchdog computer operating properly (COP) reset running from dedicated 1-kHz internal clock source or bus clock – Low-voltage detection with reset or interrupt; selectable trip points – Illegal opcode and illegal address detection with reset – Flash memory block protection • Development Support – Single-wire background debug interface – Breakpoint capability to allow single breakpoint setting during in-circuit debugging (plus three more breakpoints in on-chip debug module) – On-chip in-circuit emulator (ICE) debug module containing three comparators and nine trigger modes. Eight deep FIFO for storing change-of-flow addresses and event-only data. Debug module supports both tag and force breakpoints • Peripherals – IPC — Interrupt Priority Controller with 4 programmable interrupt priority levels – ADC — 13-channel, 12-bit resolution; 2.5 s conversion time; automatic compare function; 1.7 mV/C temperature sensor; internal bandgap reference channel; operation in stop3 28-SOIC Case 751F-05 – PGA — Differential programmable gain amplifier with programmable gain (x1, x2, x4, x8, x16, or x32) – HSCMP — Three fast analog comparators with positive and negative inputs; separately selectable interrupt on rising and falling comparator output; filtering; windowing; HSCMP1 and HSCMP2 outputs can be optionally routed to FTM1 module; runs in stop3 – DAC — Three 5-bit digital to analog convertor used as a 32-tap voltage reference for each comparator – PDB — Two programmable delay blocks: PDB1 synchronizes PWM with samples of ADC; PDB2 synchronizes PWM with comparing window of analog comparators – SCI — Full duplex non-return to zero (NRZ); LIN master e.


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