Document
CAT1024, CAT1025
Supervisory Circuits with EEPROM Serial 2k-bit I2C and Manual Reset
Description The CAT1024 and CAT1025 are complete memory and supervisory
solutions for microcontroller−based systems. A 2k−bit serial EEPROM memory and a system power supervisor with brown−out protection are integrated together in low power CMOS technology. Memory interface is via a 400 kHz I2C bus.
The CAT1025 provides a precision VCC sense circuit and two open drain outputs: one (RESET) drives high and the other (RESET) drives low whenever VCC falls below the reset threshold voltage. The CAT1025 also has a Write Protect input (WP). Write operations are disabled if WP is connected to a logic high.
The CAT1024 also provides a precision VCC sense circuit, but has only a RESET output and does not have a Write Protect input.
All supervisors have a 1.6 second watchdog timer circuit that resets a system to a known state if software or a hardware glitch halts or “hangs” the system. For the CAT1024 and CAT1022, the watchdog timer monitors the SDA signal. The CAT1023 has a separate watchdog timer interrupt input pin, WDI.
The power supply monitor and reset circuit protect memory and system controllers during power up/down and against brownout conditions. Five reset threshold voltages support 5 V, 3.3 V and 3 V systems. If power supply voltages are out of tolerance reset signals become active, preventing the system microcontroller, ASIC or peripherals from operating. Reset signals become inactive typically 200 ms after the supply voltage exceeds the reset threshold level. With both active high and low reset signals, interface to microcontrollers and other ICs is simple. In addition, the RESET pin or a separate input, MR, can be used as an input for push−button manual reset capability.
The CAT1024/25 memory features a 16−byte page. In addition, hardware data protection is provided by a VCC sense circuit that prevents writes to memory whenever VCC falls below the reset threshold or until VCC reaches the reset threshold during power up.
Available packages include a surface mount 8−pin SOIC, 8−pin TSSOP, 8−pin TDFN and 8−pin MSOP packages. The TDFN package thickness is 0.8 mm maximum. TDFN footprint is 3 x 3 mm.
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TSSOP−8 CASE 948S
SOIC−8 CASE 751BD
MSOP−8 CASE 846AD
TDFN−8 CASE 511AL
ORDERING INFORMATION For Ordering Information details, see page 13.
Features
• Precision Power Supply Voltage Monitor
♦ 5 V, 3.3 V and 3 V Systems
♦ Five Threshold Voltage Options
• Active High or Low Reset
♦ Valid Reset Guaranteed at VCC = 1 V
• 400 kHz I2C Bus • 2.7 V to 5.5 V Operation • Low Power CMOS Technology • 16−Byte Page Write Buffer
• Built−in Inadvertent Write Protection
♦ WP Pin (CAT1025)
• 1,000,000 Program/Erase Cycles • Manual Reset Input • 100 Year Data Retention • Industrial and Extended Temperature Ranges • Green Packages Available with NiPdAu Lead Finished • These Devices are Pb−Free, Halogen Free/BFR Free
and are RoHS Compliant
© Semiconductor Components Industries, LLC, 2011
1
May, 2018 − Rev. 21
Publication Order Number: CAT1024/D
CAT1024, CAT1025
Table 1. THRESHOLD VOLTAGE OPTION
Part Dash Number
Minimum Threshold
Maximum Threshold
−45
4.50
4.75
−42
4.25
4.50
−30
3.00
3.15
−28
2.85
3.00
−25
2.55
2.70
EXTERNAL LOAD
VCC VSS
BLOCK DIAGRAM
DOUT ACK
WORDADDRESS BU F F E R S
SENSEAMPS SHIFT REGISTERS
COLUMN DECODERS
SDA WP*
STA RT/ STOP LOGIC
CONTROL LOGIC
XDEC
2kbit EEPROM
DATA IN STORAGE
HIGHVOLTAGE/ TIMING CONTROL
RESET Controller
STATE COUNTERS
SCL
Precision
SLAVE
MR
Vcc Monitor
ADDRESS
COMPARATORS
*CAT1025 Only
RESET* RESET
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CAT1024, CAT1025
DIP Package (L) SOIC Package (W) TSSOP Package (Y) MSOP Package (Z)
PIN CONFIGURATION
MR RESET
NC VSS
1
8
2
7
CAT1024
3
6
4
5
VCC NC SCL SDA
(Bottom View) TDFN Package: 3 mm x 3 mm 0.8mm maximum height − (ZD4)
VCC 8
1 MR
NC 7
2 RESET
CAT1024
SCL 6
3 NC
SDA 5
4 VSS
MR RESET RESET
VSS
1
8
2
7
CAT1025
3
6
4
5
VCC WP SCL SDA
VCC 8
1 MR
WDI 7
2 RESET
CAT1025
SCL 6
3 RESET
SDA 5
4 VSS
PIN DESCRIPTION
RESET/RESET: RESET OUTPUTs (RESET CAT1025 Only)
These are open drain pins and RESET can be used as a manual reset trigger input. By forcing a reset condition on the pin the device will initiate and maintain a reset condition. The RESET pin must be connected through a pull−down resistor, and the RESET pin must be connected through a pull−up resistor.
SDA: SERIAL DATA ADDRESS The bidirectional serial data/address pin is used to transfer
all data into and out of the device. The SDA pin is an open drain output and can be wire−ORed with other open drain or open collector outputs.
SCL: SERIAL CLOCK Serial clock input.
MR: MANUAL RESET INPUT Manual Reset input is a debounced input that can be
connected to an external source for Manual Reset. Pulling the MR input low will generate a Reset conditio.