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NCV5701A, NCV5701B, NCV5701C
High Current IGBT Gate Drivers
The NCV5701A, NCV5701B and NCV5701C are high−current, high−performance stand−alone IGBT drivers for high power applications that include solar inverters, motor control and uninterruptible power supplies. The devices offer a cost−effective solution by eliminating external output buffer. Devices protection features include accurate Under−voltage−lockout (UVLO), desaturation protection (DESAT) and Active Low FAULT output. The drivers also feature an accurate 5.0 V output. The drivers are designed to accommodate a wide voltage range of bias supplies including unipolar and NCV5701B even bipolar voltages.
Depending on the pin configuration the devices also include Active Miller Clamp (NCV5701A) and separate high and low (VOH and VOL) driver outputs for system design convenience (NCV5701C).
All three available pin configuration variants have 8−pin SOIC package.
Features
• High Current Output (+4/−6 A) at IGBT Miller Plateau voltages • Low Output Impedance for Enhanced IGBT Driving • Short Propagation Delay with Accurate Matching • Direct Interface to Digital Isolator/Opto−coupler/Pulse Transformer
for Isolated Drive, Logic Compatibility for Non−isolated Drive
• DESAT Protection with Programmable Delay • Tight UVLO Thresholds for Bias Flexibility • Wide Bias Voltage Range • NCV Prefix for Automotive and Other Applications Requiring
Unique Site and Control Change Requirements; AEC−Q100 Qualified and PPAP Capable, Grade 1
• These Devices are Pb−Free, Halogen Free/BFR Free and are RoHS
Compliant
NCV5701A Features
• Active Miller Clamp to Prevent Spurious Gate Turn−on
NCV5701B Features
• Negative Output Voltage for Enhanced IGBT Driving
NCV5701C Features
• Separate Outputs for VOL and VOH
Typical Applications
• Motor Control • Uninterruptible Power Supplies (UPS) • Automotive Power Supplies • HEV/EV Powertrain • HEV/EV PTC Heaters
www.onsemi.com
8
1
SOIC−8 D SUFFIX CASE 751
MARKING DIAGRAM 8
NCV5701X ALYW G
1
NCV5701 = Specific Device Code
X
= A, B or C
A
= Assembly Location
L
= Wafer Lot
Y
= Year
W
= Work Week
G
= Pb−Free Package
PIN CONNECTIONS
1 VIN
2 VREF
3 FLT
4 DESAT
8 CLAMP
7 GND
6 VO
5 VCC
NCV5701A
1 VIN
2 VREF
3 FLT
4 DESAT
8 VEE
7 GND
6 VO
5 VCC
NCV5701B
1 VIN
2 VREF
3 FLT
4 DESAT
8 GND
7 VOL
6 VOH
5 VCC
NCV5701C
ORDERING INFORMATION
See detailed ordering and shipping information on page 9 of this data sheet.
© Semiconductor Components Industries, LLC, 2017
1
October, 2017 − Rev. 0
Publication Order Number: NCV5701/D
NCV5701A, NCV5701B, NCV5701C
NCV5701A
VREF DESAT
VCC
VCC
VO
CLAMP
VIN
GND
FLT
NCV5701B
VREF DESAT
VCC
VCC
VO
VIN
GND
VEE
VEE
FLT
NCV5701C
VREF DESAT
VCC
VCC
VOH VOL
VIN
GND
FLT
Figure 1. Simplified Application Schematics
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NCV5701A, NCV5701B, NCV5701C
FLT DESAT
SET
QS
Q CLR R
IDESAT-CHG
+
VDESAT-THR
-
VREF
RIN-H
VIN
VREF VCC
Bandgap
VUVLO
+
TSD
DELAY
SET
SQ R CLR Q
NCV5701A
VCC
DELAY
Ï
SET
SQ
R CLR Q
+
VMC-THR
Ï
GND Figure 2(a). Detailed Block Diagram NCV5701A
NCV5701A
VREF VIN
CLAMP
CLAMP
VCC
VREF
LDO
GND
Logic Unit
FLT
TSD
VO
VCC
UVLO
DESAT
DESAT
VCC
VO
CLAMP
Figure 2(b). Simplified Block Diagram NCV5701A
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NCV5701A, NCV5701B, NCV5701C
FLT DESAT
SET
QS
Q CLR R
IDESAT-CHG
+
VDESAT-THR
-
VREF
RIN-H
VIN
VREF VCC
Bandgap
VUVLO
+
TSD
DELAY
SET
SQ R CLR Q
NCV5701B
VCC
DELAY
VO
Ï
VEE
GND
VEE
Figure 3(a). Detailed Block Diagram NCV5701B
NCV5701B
VREF
VIN
VEE
VREF
VCC
LDO
GND
Logic Unit
FLT
TSD
VO
VCC
UVLO
DESAT
DESAT
VCC
Figure 3(b). Simplified Block Diagram NCV5701B
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NCV5701A, NCV5701B, NCV5701C
FLT DESAT
SET
QS
Q CLR R
IDESAT-CHG
+
VDESAT-THR
-
VREF
RIN-H
VIN
VREF VCC
Bandgap
VUVLO
+
TSD
DELAY
SET
SQ R CLR Q
NCV5701C
VCC
VOH
DELAY
Ï
VOL
GND Figure 4(a). Detailed Block Diagram NCV5701C
NCV5701C
VREF
VIN
GND
VCC
VREF
LDO
VOL
Logic Unit
FLT
TSD
VOH
VCC
UVLO
DESAT
DESAT
VCC
Figure 4(b). Simplified Block Diagram NCV5701C
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NCV5701A, NCV5701B, NCV5701C
Table 1. PIN FUNCTION DESCRIPTION
Pin Name
No.
I/O/x
Description
VIN
1
I
Input signal to control the output. In applications which require galvanic isolation, VIN is generat-
ed at the opto output, the pulse transformer secondary or the digital isolator output. There is a
signal inversion from VIN to VO (VOH/VOL). VIN is internally clamped to 5.5 V and has a pull−
up resistor of 1 MW to ensure that an output is low in the absence of an input signal. A minimum
pulse−width is required at VIN before VO (VOH/VOL) is activated.
VREF
2
O
5 V Reference generated within the driver is brought out to this pin for external bypassing and
for powering low bias circuits (such as digital isolators).
FLT
3
O
Fault output (active low) that allows communication to the main controller that the d.