Document
FAN54161
Battery Charging IC, 98% Efficient, Safe 6 A Direct with Regulation and Protection
The FAN54161UCX is a low loss direct charger which charges the battery safely at 6 A and provides active protection, regulation and monitoring features.
Integrated Protection and Regulation features control a pair of MOSFETs to ensure that the FAN54161UCX output voltage and current stay within a safe programmed operating range. Configurable hardware based safety features turn off the MOSFET in the event of a fault and notify the system.
An integrated 10−bit Analog−to−Digital Converter (ADC) provides real−time monitoring of input, output voltage, currents and temperature so that the system host or microcontroller can effectively use this information to optimize adapter and charger configuration.
Features
• Integrated Back−to−Back Common Source N−channel MOSFETs
with Combined RON = 11 mW
• Maximum Input Voltage Tolerance of +22 V • Reverse Input Voltage Tolerance of −2 V • External N−channel MOSFET Drive Capability with Tolerance up to
+32 V
• Regulation Modes
♦ Charge Current ♦ Input Current ♦ Output Voltage ♦ Battery Cell Voltage
• Hardware−based Safety Protections
♦ Input Over−Voltage ♦ Input Under−Voltage ♦ Output Over−Voltage ♦ Input Over−Current ♦ Die Over−Temperature ♦ Internal Switch Short
• 10−bit High−accuracy ADC
Typical Applications
• Mobile Devices • Tablets
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WLCSP42 CASE 567TY
MARKING DIAGRAM
1 2 KK XYZ
12 = Specific Device Code KK = Lot Run Code X = Year Code Y = 2−Weeks Date Code Z = Assembly Plant Code
ORDERING INFORMATION
See detailed ordering and shipping information on page 2 of this data sheet.
© Semiconductor Components Industries, LLC, 2017
1
July, 2018 − Rev.4
Publication Order Number: FAN54161/D
FAN54161
Block Diagram and Application Schematic
FAN54511A
/INT
SW
SCL SDA VBUS
Power−Path Switching Charger
SYS
Body Control
VBAT
System Load
FDMC8321L
VBUS
7
CBUS
2.4V RPU
RNTCBUS
RLIMIT
System Host
VBUS
FAULT PROTECTION IBUS OCP IBUS RCB VBUS OVP
VBUS UVLO
VOUT OVP VDROP OVP
IC Temp Battery Temp Watchdog Timer
RVBUS_PD
OVP_C
CHARGE PUMP GATE DRIVER
VUSB OVP VUSB UVLO
VBUS OVP VBUS UVLO IBUSREG CC IBUS OCP IBUS RCB
VUSB
TS_BUS
INPUT THERMAL PROTECTION
INT_N SCL SDA RESET_N ADR
I2C INTERFACE LOGIC AND CONTROL
IC THERMAL PROTECTION
FAN54161
GATE DRIVER CHARGE PUMP OSCILLATOR
REGULATION LOOPS
VOREG CV VBATREG CV
IBATREG CC IBUSREG CC
VOUT PMID
14
COUT
7
VDROP OVP VDROP Alarm
9 Channel 10−Bit ADC
GND
VOREG CV VOUT OVP
VSNSP
VBATREG CV CONTROL VSNSN
BATTERY THERMAL
TS_BAT
PROTECTION
PACK+ Battery Pack PSNS+
+
2.4V PSNS− RPU Protection
NTC
IBATREG CC
SRP SRN
PACK− RSENSE
FFG1040
INT_N VBAT
SCL
SDA
Fuel Gauge
SRP
AGND/SRN
Figure 1. FAN54161, External FET, Switching Charger, Battery Pack with Exposed Cell, and External Fuel Gauge
RECOMMENDED COMPONENTS
Component
Manufacturer
CBUS CBUS (alternative)
COUT RSENSE RSENSE (alternative)
Murata TDK TDK
Ohmite Ohmite
Part Number GRM188R61E105K C1608X5R1E105K C1608X5R0J226M MCS1632R010FER MCS1632R005FER
Value 1.0 mF 1.0 mF 22 mF 0.01 (±1%) Ohm 0.005 (±1%) Ohm
Case Size 0603 (1608 metric) 0603 (1608 metric) 0603 (1608 metric) 1206 (3216 metric) 1206 (3216 metric)
Rating 25 V 25 V 6.3 V 1W 1W
ORDERING INFORMATION
Part Number
Temperature Range
FAN54161UCX
−40°C to +85°C
Package 2.78 x 3.06 mm, 42−Bump WLCSP
Packing Method Tape and Reel
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FAN54161
Pin Connections and Functional Description
VUSB A1
OVP_C A2
VOUT A3
VOUT A4
SCL TS_BUS VOUT VOUT
B1
B2
B3
B4
PMID A5
PMID B5
VBUS A6
VBUS B6
SDA
INT_N VOUT VOUT PMID VBUS
C1
C2
C3
C4
C5
C6
TS_BAT RESET_N VOUT
D1
D2
D3
VOUT D4
PMID D5
VBUS D6
SRN E1
ADR E2
VOUT E3
VOUT E4
PMID E5
VBUS E6
SRP
GND
VOUT
VOUT
PMID
VBUS
F1
F2
F3
F4
F5
F6
SNSN G1
SNSP G2
VOUT G3
VOUT G4
PMID G5
VBUS G6
Figure 2. WLCSP−42 Pin Assignments
Table 1. PIN DESCRIPTIONS
Name
Position
Type
ADR
E2
Digital Input
Description
I2C Slave Device Address Selection Pin Refer to I2C Interface section for details ADR logic level must be set before releasing RESET_N high. Recommend connecting this pin to the appropriate logic level before power is applied (VBUS or VOUT).
GND
F2
Ground Device Ground
Connect to the ground node in the PCB.
INT_N
C2
Open−Drain Interrupt Output (Active Low)
Digital Output Pull−up with 100 kW resistor to logic supply voltage. When an un−masked interrupt bit is
set this pin will assert low.
Connect to GND if not used.
RESET_N
D2
Digital Input
Reset Input (Active Low)
0 (Logic Low) – IC held in reset condition (lowest power state), switch is open, ADC is disabled, and I2C communication is not available. 1 (Logic High) – IC logic allowed to operate, switch closed if SW_EN = 1; ADC enabled if ADC_EN = 1. If not used, it is recommended to pull−up to VOUT.
SCL SDA
B1
Digital I.