HEX D-TYPE FLIP-FLOPS
D Inputs Are TTL-Voltage Compatible D Contain Six Flip-Flops With Single-Rail
Outputs
D Applications Include:
– Buffer/S...
Description
D Inputs Are TTL-Voltage Compatible D Contain Six Flip-Flops With Single-Rail
Outputs
D Applications Include:
– Buffer/Storage Registers – Shift Registers – Pattern Generators
D Latch-Up Performance Exceeds 250 mA Per
JESD 17
D ESD Protection Exceeds JESD 22
– 2000-V Human-Body Model (A114-A) – 200-V Machine Model (A115-A) – 1000-V Charged-Device Model (C101)
description
These positive-edge-triggered D-type flip-flops have a direct clear (CLR) input.
Information at the data (D) inputs meeting the setup time requirements is transferred to the outputs on the positive-going edge of the clock (CLK) pulse. Clock triggering occurs at a particular voltage level and is not directly related to the transition time of the positive-going edge of CLK. When CLK is at either the high or low level, the D input has no effect at the output.
SN54AHCT174, SN74AHCT174 HEX D-TYPE FLIP-FLOPS WITH CLEAR
SCLS419F – JUNE 1998 – REVISED APRIL 2002
SN54AHCT174 . . . J OR W PACKAGE SN74AHCT174 . . . D, DB, DGV, N, NS, OR PW PACKAGE
(TOP VIEW)
CLR 1 1Q 2 1D 3 2D 4 2Q 5 3D 6 3Q 7
GND 8
16 VCC 15 6Q 14 6D 13 5D 12 5Q 11 4D 10 4Q 9 CLK
SN54AHCT174 . . . FK PACKAGE (TOP VIEW)
1Q CLR NC VCC 6Q
3 2 1 20 19
1D 4
18 6D
2D 5
17 5D
NC 6
16 NC
2Q 7
15 5Q
3D 8
14 4D
9 10 11 12 13
3Q GND
NC CLK
4Q
NC – No internal connection
ORDERING INFORMATION
TA
PACKAGE†
ORDERABLE PART NUMBER
TOP-SIDE MARKING
PDIP – N
Tube
SN74AHCT174N
SN74AHCT174N
SOIC – D
Tube Tape and reel
SN74AHCT174D SN74AHCT174D...
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