SN74AHCT125-EP

D Controlled Baseline − One Assembly/Test Site, One Fabrication Site D Extended Temperature Performance of −40°C to 125°C D Enhanced Diminishing Manufacturing Sources (DMS) Support D Enhanced Product-Change Notification D Qualification Pedigree† † Component qualification in accordance with JEDEC and industry standards to ensure reliable operation over an extended temperature range. This includes, but is not limited to, Highly Accelerated Stress Test (HAST) or biased 85/85, temperature cycle, autoclave or unbiased HAST, electromigration, bond intermetallic life, and mold compound life. Such qualification testing should not be viewed as justifying use of this component beyond specified performance and environmental limits. SN74AHCT125ĆEP QUADRUPLE BUS BUFFER GATE WITH 3ĆSTATE OUTPUTS SCLS549 − DECEMBER 2003 D ESD Protection Exceeds 2000 V Per MIL-STD-883, Method 3015; Exceeds 200 V Using Machine Model (C = 200 pF, R = 0) D Inputs Are TTL-Voltage Compatible D OR PW PACKAGE (TOP VIEW) 1OE 1 1A 2 1Y 3 2OE 4 2A 5 2Y 6 GND 7 14 VCC 13 4OE 12 4A 11 4Y 10 3OE 9 3A 8 3Y description/ordering information The SN74AHCT125 is a quadruple bus buffer gate featuring independent line drivers with 3-state outputs. Each output is disabled when the associated output-enable (OE) input is high. When OE is low, the respective gate passes the data from the A input to its Y output. To ensure the high-impedance state during power up or power down, OE should be tied to VCC through a pullup resistor;...