Document
TLV1544C, TLV1544I, TLV1548C, TLV1548I, TLV1548M
LOW-VOLTAGE 10-BIT ANALOG-TO-DIGITAL CONVERTERS WITH SERIAL CONTROL AND 4/8 ANALOG INPUTS
SLAS139C – DECEMBER 1996 – REVISED JANUARY 1999
D Conversion Time ≤ 10 µs D 10-Bit-Resolution ADC D Programmable Power-Down
Mode . . . 1 µA
D Wide Range Single-Supply Operation of
2.7 V dc to 5.5 V dc
D Analog Input Range of 0 V to VCC D Built-in Analog Multiplexer with 8 Analog
Input Channels
D TMS320 DSP and Microprocessor SPI and
QSPI Compatible Serial Interfaces
D End-of-Conversion (EOC) Flag D Inherent Sample-and-Hold Function D Built-In Self-Test Modes D Programmable Power and Conversion Rate D Asynchronous Start of Conversion for
Extended Sampling
D Hardware I/O Clock Phase Adjust Input
description
The TLV1544 and TLV1548 are CMOS 10-bit switched-capacitor successive-approximation (SAR) analog-to-digital (A/D) converters. Each device has a chip select (CS), input-output clock (I/O CLK), data input (DATA IN) and serial data output (DATA OUT) that provide a direct 4-wire synchronous serial peripheral interface (SPI™, QSPI™) port of a host microprocessor. When interfacing with a TMS320 DSP, an additional frame sync signal (FS) indicates the start of a serial data frame. The devices allow high-speed data transfers from the host. The INV CLK input provides further timing flexibility for the serial interface.
DATA OUT DATA IN I/O CLK EOC VCC A0 A1 A2
A0 A1 A2 A3 A4 A5 A6 A7 CSTART GND
D OR PW PACKAGE (TOP VIEW)
1
16
2
15
3
14
4
13
5
12
6
11
7
10
8
9
DB OR J PACKAGE (TOP VIEW)
1
20
2
19
3
18
4
17
5
16
6
15
7
14
8
13
9
12
10
11
FK PACKAGE (TOP VIEW)
CS REF+ REF– FS INV CLK GND CSTART A3
VCC EOC I/O CLK DATA IN DATA OUT CS REF+ REF– FS INV CLK
A2 A1 A0 VCC EOC
3 2 1 20 19
A3 4
18 I/O CLK
A4 5
17 DATA IN
A5 6
16 DATA OUT
A6 7
15 CS
A7 8
14 REF+
9 10 11 12 13
CSTART GND
INV CLK FS
REF–
In addition to a high-speed converter and versatile control capability, the device has an on-chip 11-channel multiplexer that can select any one of eight analog inputs or any one of three internal self-test voltages. The sample-and-hold function is automatic except for the extended sampling cycle, where the sampling cycle is started by the falling edge of asynchronous CSTART. At the end of the A/D conversion, the end-of-conversion (EOC) output goes high to indicate that the conversion is complete. The TLV1544 and TLV1548 are designed to operate with a wide range of supply voltages with very low power consumption. The power saving feature is further enhanced with a software-programmed power-down mode and conversion rate. The converter incorporated in the device features differential high-impedance reference inputs that facilitate ratiometric conversion, scaling, and isolation of analog circuitry from logic and supply noise. A switched-capacitor design allows low-error conversion over the full operating temperature range.
SPI and QSPI are registered trademarks of Motorola, Inc.
PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters.
• POST OFFICE BOX 655303 DALLAS, TEXAS 75265
Copyright © 1999, Texas Instruments Incorporated 1
TLV1544C, TLV1544I, TLV1548C, TLV1548I, TLV1548M LOW-VOLTAGE 10-BIT ANALOG-TO-DIGITAL CONVERTERS WITH SERIAL CONTROL AND 4/8 ANALOG INPUTS
SLAS139C – DECEMBER 1996 – REVISED JANUARY 1999
description (continued)
The TLV1544 has four analog input channels while the TLV1548 has eight analog input channels. The TLV1544C and TLV1548C are characterized for operation from 0°C to 70°C. The TLV1544I and TLV1548I are characterized for operation over the full industrial temperature range of –40°C to 85°C. The TLV1548M is characterized for operation over the full military temperature range of –55°C to 125°C.
functional block diagram
A0–A7 1–8 REF+ 14
Self-Test Reference
Sample and
Hold Function
CLOCK
10-Bit ADC (Switch Capacitors)
Analog MUX
Output Data Register
10-to-1 Data Selector
16 DATA OUT
13 REF–
17 DATA IN
Input Data Register
Control Logic and
I/O Counters
19 EOC
12 FS
15 CS 9 CSTART 11 INV CLK
18 I/O CLK
Terminals shown are for the DB package.
TA
0°C to 70°C – 40°C to 85°C – 55°C to 125°C
(DB) TLV1548CDB TLV1548IDB
AVAILABLE OPTIONS
PACKAGE
SMALL OUTLINE
(D)
(PW)
TLV1544CD
TLV1544CPW
TLV1544ID
TLV1544IPW
(J) TLV1548MJ
(FK) TLV1548MFK
DISSIPATION RATING TABLE
PACKAGE
TA ≤ 25°C POWER RATING
DERATING FACTOR† ABOVE TA = 25°C
TA = 70°C POWER RATING
TA = 85°C POWER RATING
TA = 125°C POWER RATING
DB
785 mW
8.7 mW/°C
393 mW
261 mW
—
D
799 mW
8.9 mW/°C
399 mW
266 mW
—
PW
604 mW
6.7 mW/°C
302 mW
201 mW
—
J
1894 mW
15.1 mW/°C
1212 mW
985 mW
379 mW
FK
1375 mW
11.0 mW/°C
880 mW
715 mW
275 mW
† This is the inverse of the tra.