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SN65LVCP404 Dataheets PDF



Part Number SN65LVCP404
Manufacturers Texas Instruments
Logo Texas Instruments
Description Gigabit 4x4 CROSSPOINT SWITCH
Datasheet SN65LVCP404 DatasheetSN65LVCP404 Datasheet (PDF)

SN65LVCP404 www.ti.com .. SLLS700B – MARCH 2007 – REVISED JANUARY 2009 Gigabit 4x4 CROSSPOINT SWITCH FEATURES 1 • Up to 4.25 Gbps Operation • Non-blocking Architecture Allows Each Output to be Connected to Any Input • 30 ps of Deterministic Jitter • Selectable Transmit Pre-Emphasis Per Lane • Selectable Receive Equalization • Available Packaging 48 Pi.

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SN65LVCP404 www.ti.com ................................................................................................................................................... SLLS700B – MARCH 2007 – REVISED JANUARY 2009 Gigabit 4x4 CROSSPOINT SWITCH FEATURES 1 • Up to 4.25 Gbps Operation • Non-blocking Architecture Allows Each Output to be Connected to Any Input • 30 ps of Deterministic Jitter • Selectable Transmit Pre-Emphasis Per Lane • Selectable Receive Equalization • Available Packaging 48 Pin QFN • Propagation Delay Times: 500 ps Typical • Inputs Electrically Compatible With CML Signal Levels • Operates From a Single 3.3-V Supply • Ability to 3-STATE ouputs • Low Power: 560 mW • Integrated Termination Resistors APPLICATIONS • Clock Buffering/Clock MUXing • Wireless Base Stations • High-Speed Network Routing • Telecom/Datacom • XAUI 802.3ae Protocol Backplane Redundancy DESCRIPTION The SN65LVCP404 is a 4x4 non-blocking crosspoint switch in a flow-through pin-out allowing for ease in PCB layout. VML signaling is used to achieve a high-speed data throughput while using low power. Each of the output drivers includes a 4:1 multiplexer to allow any input to be routed to any output. Internal signal paths are fully differential to achieve the high signaling speeds while maintaining low signal skews. The SN65LVCP404 incorporates 100-Ω termination resistors for those applications where board space is a premium. Built-in transmit pre-emphasis and receive equalization for superior signal integrity performance. S30 13 S31 14 GND 15 4A 16 4B 17 VCC 18 S40 19 S41 20 P41 21 P42 22 P31 23 P32 24 The SN65LVCP404 is characterized for operation from -40°C to 85°C. 48 S11 47 S10 46 VCC 45 1DE 44 P12 43 P11 42 GND 41 1Y 40 1Z 39 VCC 38 2DE 37 3DE S20 1 S21 2 1A 3 1B 4 GND 5 2A 6 2B 7 VCC 8 3A 9 3B 10 EQ 11 VBB 12 36 P22 35 P21 34 2Y 33 2Z 32 GND 31 3Y 30 3Z 29 VCC 28 4Y 27 4Z 26 GND 25 4DE 1 Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet. PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of the Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters. Copyright © 2007–2009, Texas Instruments Incorporated SN65LVCP404 SLLS700B – MARCH 2007 – REVISED JANUARY 2009 ................................................................................................................................................... www.ti.com These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam during storage or handling to prevent electrostatic damage to the MOS gates. LOGIC DIAGRAM TERMINAL FUNCTIONS TERMINAL NAME NO. High Speed I/O xA 3, 6, 9, 16 xB 4, 7, 10, 17 xY 41, 34, 31, 28 xZ 40, 33, 30, 27 Control Signals TYPE Differential Inputs (with 50-Ω termination to Vbb) xA=P; xB=N Differential Output xY=P; xZ=N xDE 45, 38, 37, 25 Input S10 - S41 1, 2, 13, 14, 19, 20, 47, 48 Input; S1x = Channel 1 bit one P11-P42 43, 44, 35, 36, 23, 24, 21, 22 Input; P1x- Channel 1 bit one EQ 11 Input; Selection for receive equalization setting Power Supply VCC 8, 18, 29, 39, 46 Power GND 5, 15, 26, 32, 42 Thermal Pad VBB 12 Input DESCRIPTION Line Side Differential Inputs CML compatible Switch Side Differential Outputs. VML Data Enable; Active Low; LVTTL; When not enabled the ouput is in 3-STATE mode for power savings Switching Selection; LVTTL Output Preemphasis Control; LVTTL EQ = 1 (default) is for the 5 dB setting, EQ = 0 is for the 12 dB setting Power Supply 3.3v ±5% The ground center pad of the package must be connected to GND plane. Receiver input biasing voltage. For ac coupling, VBB should be left floating for optimal bias value. For dc coupling, VBB can driven to change the common mode. VBB should not be tied to ground. 2 Submit Documentation Feedback Copyright © 2007–2009, Texas Instruments Incorporated Product Folder Link(s): SN65LVCP404 SN65LVCP404 www.ti.com ................................................................................................................................................... SLLS700B – MARCH 2007 – REVISED JANUARY 2009 EQUIVALENT INPUT AND OUTPUT SCHEMATIC DIAGRAMS VCC IN+ RT(SE) = 50 W VCC Gain Stage + EQ RBBDC RT(SE) = 50 W IN− VBB LineEndTermination ESD Self−Biasing Network Figure 1. Equivalent Input Circuit Design OUT+ 49.9 W OUT− 49.9 W 1 pF VOCM Figure 2. Common-Mode Output Voltage Test Circuit OUTPUT CHANNEL 1 CONTROL PINS INPUT SELECTED S10 S11 1Y/1Z 0 0 1A/1B 0 1 2A/2B 1 0 3A/3B 1 1 4A/4B Table 1. CROSSPOINT LOGIC TABLES OUTPUT CHANNEL 2 CONTROL PINS INPUT SELECTED S20 S21 2Y/2Z 0 0 1A/1B 0 1 2.


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