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TMS320DM8165 Dataheets PDF



Part Number TMS320DM8165
Manufacturers Texas Instruments
Logo Texas Instruments
Description Digital Media Processors
Datasheet TMS320DM8165 DatasheetTMS320DM8165 Datasheet (PDF)

Product Folder Sample & Buy Technical Documents Tools & Software Support & Community TMS320DM8168, TMS320DM8167 TMS320DM8165 SPRS614F – MARCH 2011 – REVISED MARCH 2015 TMS320DM816x DaVinci™ Digital Media Processors 1 Device Overview 1.1 Features 1 • High-Performance DaVinci Digital Media Processors – ARM® Cortex™-A8 RISC Processor • Up to 1.20 GHz – C674x™ VLIW DSP • Up to 1 GHz • Up to 8000 MIPS and 6000 MFLOPS • Fully Software-Compatible with C67x+ and C64x+™ • ARM Cortex-A8 Core – ARMv.

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Product Folder Sample & Buy Technical Documents Tools & Software Support & Community TMS320DM8168, TMS320DM8167 TMS320DM8165 SPRS614F – MARCH 2011 – REVISED MARCH 2015 TMS320DM816x DaVinci™ Digital Media Processors 1 Device Overview 1.1 Features 1 • High-Performance DaVinci Digital Media Processors – ARM® Cortex™-A8 RISC Processor • Up to 1.20 GHz – C674x™ VLIW DSP • Up to 1 GHz • Up to 8000 MIPS and 6000 MFLOPS • Fully Software-Compatible with C67x+ and C64x+™ • ARM Cortex-A8 Core – ARMv7 Architecture • In-Order, Dual-Issue, Superscalar Processor Core • NEON™ Multimedia Architecture – Supports Integer and Floating Point (VFPv3IEEE754 Compliant) • Jazelle® RCT Execution Environment • ARM Cortex-A8 Memory Architecture – 32-KB Instruction and Data Caches – 256-KB L2 Cache – 64-KB RAM, 48-KB of Boot ROM • TMS320C674x Floating-Point VLIW DSP – 64 General-Purpose Registers (32-Bit) – Six ALU (32-Bit and 40-Bit) Functional Units • Supports 32-Bit Integer, SP (IEEE Single Precision, 32-Bit) and DP (IEEE Double Precision, 64-Bit) Floating Point • Supports up to Four SP Adds Per Clock and Four DP Adds Every Two Clocks • Supports up to Two Floating-Point (SP or DP) Approximate Reciprocal or Square Root Operations Per Cycle – Two Multiply Functional Units • Mixed-Precision IEEE Floating-Point Multiply Supported up to: – 2 SP x SP → SP Per Clock – 2 SP x SP → DP Every Two Clocks – 2 SP x DP → DP Every Three Clocks – 2 DP x DP → DP Every Four Clocks • Fixed-Point Multiply Supports Two 32 x 32 Multiplies, Four 16 x 16-Bit Multiplies Including Complex Multiplies, or Eight 8 x 8Bit Multiplies per Clock Cycle • C674x Two-Level Memory Architecture – 32-KB L1P and L1D RAM and Cache – 256-KB L2 Unified Mapped RAM and Caches 1 • System Memory Management Unit (System MMU) – Maps C674x DSP and EMDA TCB Memory Accesses to System Addresses • 512KB of On-Chip Memory Controller (OCMC) RAM • Media Controller – Manages HDVPSS and HDVICP2 Modules • Up to Three Programmable High-Definition Video Image Coprocessing (HDVICP2) Engines – Encode, Decode, Transcode Operations – H.264, MPEG-2, VC-1, MPEG-4 SP and ASP • SGX530 3D Graphics Engine (Available Only on the DM8168 Device) – Delivers up to 30 MTriangles per Second – Universal Scalable Shader Engine – Direct3D® Mobile, OpenGL® ES 1.1 and 2.0, OpenVG™ 1.1, OpenMax™ API Support – Advanced Geometry DMA Driven Operation – Programmable HQ Image Anti-Aliasing • Endianness – ARM, DSP Instructions and Data – Little Endian • HD Video Processing Subsystem (HDVPSS) – Two 165-MHz HD Video Capture Channels • One 16-Bit or 24-Bit and One 16-Bit Channel • Each Channel Splittable Into Dual 8-Bit Capture Channels – Two 165-MHz HD Video Display Channels • One 16-Bit, 24-Bit, 30-Bit Channel and One 16-Bit Channel – Simultaneous SD and HD Analog Output – Digital HDMI 1.3 Transmitter with PHY with HDCP up to 165-MHz Pixel Clock – Three Graphics Layers • Dual 32-Bit DDR2 and DDR3 SDRAM Interfaces – Supports up to DDR2-800 and DDR3-1600 – Up to Eight x8 Devices Total – 2GB of Total Address Space – Dynamic Memory Manager (DMM) • Programmable Multi-Zone Memory Mapping and Interleaving • Enables Efficient 2D Block Accesses • Supports Tiled Objects in 0°, 90°, 180°, or 270° Orientation and Mirroring • Optimizes Interlaced Accesses • One PCI Express® (PCIe) 2.0 Port with Integrated PHY An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications, intellectual property matters and other important disclaimers. PRODUCTION DATA. TMS320DM8168, TMS320DM8167 TMS320DM8165 SPRS614F – MARCH 2011 – REVISED MARCH 2015 – Single Port with 1 or 2 Lanes at 5.0 GT per Second – Configurable as Root Complex or Endpoint • Serial ATA (SATA) 3.0 Gbps Controller with Integrated PHYs – Direct Interface for Two Hard Disk Drives – Hardware-Assisted Native Command Queuing (NCQ) from up to 32 Entries – Supports Port Multiplier and Command-Based Switching • Two 10 Mbps, 100 Mbps, and 1000 Mbps Ethernet MACs (EMAC) – IEEE 802.3 Compliant (3.3-V I/O Only) – MII and GMII Media Independent Interfaces – Management Data I/O (MDIO) Module • Dual USB 2.0 Ports with Integrated PHYs – USB 2.0 High-Speed and Full-Speed Client – USB 2.0 High-Speed, Full-Speed, and Low- Speed Host – Supports Endpoints 0-15 • General-Purpose Memory Controller (GPMC) – 8-Bit and 16-Bit Multiplexed Address and Data Bus – Up to 6 Chip Selects with up to 256-MB Address Space per Chip Select Pin – Glueless Interface to NOR Flash, NAND Flash (with BCH and Hamming Error Code Detection), SRAM and Pseudo-SRAM – Error Locator Module (ELM) Outside of GPMC to Provide up to 16-Bit and 512-Byte Hardware ECC for NAND – Flexible Asynchronous Protocol Control for Interface to FPGA, CPLD, ASICs • En.


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